TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

16

POST OFFICE BOX 655303

MII frame format

The default or IDLE state of the MII is a logic 1. All 3-state drivers are disabled and the PHY pullup resistor pulls

the management data input/output (MDIO) line to a logic 1. Before initiating any other transaction, the station

management entity sends a preamble sequence of contiguous logic-1 bits on MDIO with 32 corresponding

cycles on MDCLK. This sequence provides the PHY a pattern to use to establish synchronization. A PHY

observes the sequence of 32 contiguous 1 bits on MDIO with 32 corresponding cycles on MDCLK before

responding to any other transactions. See Figures 5 and 6 for MII frame formats.

Start Delimiter

Operation Code

PHY Address

Register Address

Turnaround

Data

01

10

AAAAA

RRRRR

10

DDDD.DDDD.DDDD.DDDD

Figure 5. MII Read Frame Format

Start Delimiter

Operation Code

PHY Address

Register Address

Turnaround

Data

01

01

AAAAA

RRRRR

10

DDDD.DDDD.DDDD.DDDD

Figure 6. MII Write Frame Format

start delimiter

The start of a frame is indicated by a 01 pattern. This pattern specifies transitions from the default logic-1 line

state to 0 and then back to 1.

operation code

The operation code for a read is 10, and the code for a write is 01.

PHY address

The PHY address is five bits, providing 32 unique PHY addresses. The first PHY address bit transmitted and

received is the most significant bit of the address. The TNETE2101 address is set using

CDEVSEL0–CDEVSEL2, CDEVSEL 3 (SLINK), and CDEVSEL4 (MCOL).

register address

The register address is 5 bits, providing 32 individual registers to be addressed within each PHY. See Figure 4

for the addresses of individual registers.

turnaround

An idle-bit time, during which no device actively drives the MDIO signal, is inserted between the register address

field and the data field of a read frame to avoid contention. During a read frame, the PHY drives a 0 bit onto MDIO

for the bit time that follows the idle bit and precedes the data field. During a write frame, this field consists of

a 1 bit followed by a 0 bit.

data

The data field is 16 bits. The first data bit transmitted and received is the most significant bit of the data payload.