TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

13

POST OFFICE BOX 655303

PHY link establishment (continued)

SLINK

CDUPLEX

CSPEED

CAUTONEG

1200 ms MAX

750 ms MIN

Figure 3. External Autonegotiation Configuration and Status

Autonegotiation, duplex, and speed also can be controlled through the PHY register 0, GEN_ctl. These bits,

AUTOENB (bit 12), SPEED (bit 13), and DUPLEX (bit 8), are similar to and work with CAUTONEG, CSPEED,

and CDUPLEX, respectively. These bits can be written and read.

When CAUTONEG is low, the AUTOENB bit remains set to a 0 and cannot be set to a 1; therefore,

autonegotiation cannot be enabled. In this case, the values read from SPEED and DUPLEX reflect the values

driven on the terminals CSPEED and CDUPLEX, respectively.

When CAUTONEG is high, AUTOENB can be set to a 1 (enabled) or a 0 (disabled). When AUTOENB is

enabled, autonegotiation is started and the SPEED and DUPLEX bits are updated to reflect the negotiated

values. When AUTOENB is disabled, autonegotiation is disabled and speed and duplex are forced to the values

written in the SPEED and DUPLEX bits.

PHY configuration

The TNETE2101 can be configured externally through the terminals or internally through the PHY registers

much like the autonegotiation terminals and register bits. Each external terminal has an equivalent PHY register

bit. Table 2 correlates the terminal with the register bit.

Table 2. External Configuration Terminal/Register Bit Correlation

TERMINAL

PIN NO.

BIT

REGISTER

BIT NO.

FUNCTION

CISOLATE

38

ISOLATE

0x0

10

Sets MII interface to high-impedance state

CPWRDOWN

32

PDOWN

0x0

11

Places PHY in power-down state

CLOOPBK

30

LOOPBK

0x0

14

Enables loopback

CREPEATER

21

REPEATER

0x11

5

Enables repeater mode

CPASS5B

37

NOENDEC

0x11

8

Disables 5B4B encoder/decoder

CFIBER

22

FIBER

0x11

10

Enables fiber interface

All of the terminals are active low and the register bits are active when set to a 1. All the register bits can be written

and read. The value read from the register bit reflects the internal configuration setting of the PHY and is derived

from the external terminal setting and the internal register bit value.