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Data Sheet

ADL5961

SERIAL PERIPHERAL INTERFACE

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PROTOCOL

The ADL5961 can be connected to an SPI bus as a peripheral

device to control and monitor several of its internal functions. See

the Serial Interface Timing Specifications section for detailed timing

requirements. The 3-wire interface with a shared data input and

output line uses 16-bit addresses to access the 8-bit wide registers.

Each SPI instruction consists of the register address followed

by one or more data bytes, with the MSB transferred first. The

ADL5961 supports single-byte read and write operations as well as

streaming read and write methods.

The 15 LSBs of the 16-bit register address define an address space

with 215 = 32,768 unique register addresses. Only a fraction of

these addresses are used by the ADL5961. The MSB is reserved to

distinguish between a write operation to the device register (MSB =

0) and a readback from the register address (MSB = 1).

READ AND WRITE METHODS

The ADL5961 supports both single register read and write methods

and streaming read and write methods, transferring data to and

from multiple registers in a single operation.

Each instruction starts with a high to low transition of the CS line.

Data is latched, starting with the MSB address bit, at each rising

edge of the clock as long as CS remains low. The instruction ends

with a low to high transition on CS. When a read instruction is

executed, the SDIO shared input and output line changes from

a high-impedance input (SDI) to a low-impedance output (SDO)

during the ½ clock cycle immediately following the rising edge on

SCLK that latched the last address bit and the next falling edge on

SCLK. SDIO returns to a high-impedance input (SDI) state when

CS is de-asserted.

Streaming read and write methods operate in autodecrement mode

only, reading and writing the next data byte to and from the register

with the address that is one lower than the previous one.

device identifiers. Register 0x20 to Register 0x26 control the analog

circuit functionality of the ADL5961. See Table 13 for further details.

Interface Configuration Register

implemented as a 4-bit palindrome with each nibble a mirror of

the other. This mirror ensures that regardless of which way data is

shifting, the ADL5961 can be programmed if device synchronization

is lost. Therefore, when writing to this address, the palindrome

is always required to eliminate any ambiguity in configuring this

Table 13. ADL5961 SPI Register Details

Addr

Name

Bits

Bit Name

Description

Reset

Access

0x00

SPI_CONFIG_A

SOFTRESET_

Soft Reset. Copy of Bit 0.

0x0

R/W

LSB_FIRST_

LSB First. Copy of Bit 1.

0x0

R/W

ASCENSION_

Address Ascension. Copy of Bit 2.

0x0

R/W

[4:3]

RESERVED

Reserved.

0x0

ASCENSION

Address Ascension. When set, causes address ascension address mode to be

enabled. When clear, addresses descend.

0x0

R/W

0: Address Autodecrement.

1: Address Autoincrement.

LSB_FIRST

LSB First. When set, causes input and output data to be oriented as LSB first.

If this bit is clear, the data is oriented as MSB first.

0x0

R/W

1: LSB First.

0: MSB First.

SOFTRESET

Soft Reset. Setting this bit initiates a reset equivalent to a hard reset with the

exception that the bits of 0x00 (this register) and the SPI state machine are

unaffected. This bit is autoclearing after the soft reset is complete.

0x0

R/W

1: Reset Asserted.

0: Reset Not Asserted.

0x01

SPI_CONFIG_B

SINGLE_INSTRUCTION

Single Instruction. When this bit is set, streaming is disabled and only one

read or write operation is performed regardless of the state of the CS line.

When this bit is clear, streaming is enabled. If this bit is set and the CS

remains asserted, the state machine resets after the data byte as if CS was

deasserted and awaits the next instruction. This forces each data byte to

0x0

R/W

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