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ADL5961ACCZ-R2 数据表(PDF) 19 Page - Analog Devices |
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ADL5961ACCZ-R2 数据表(HTML) 19 Page - Analog Devices |
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19 / 34 page ![]() Data Sheet ADL5961 THEORY OF OPERATION analog.com Rev. 0 | 19 of 34 frequency offset of a few MHz between RF and LO up to 26.5 GHz signal frequencies. The frequency divider and frequency multipliers integrated into the LO interface of the ADL5961 enable measurement sweeps beyond the frequency range supported by the LO source itself, typically a frequency synthesizer. When Bit 4 in Register 0x20 is cleared (disabling bypass mode), the LOMODE bits (Register 0x20, Bits[1:0]) can be used to program the LO multiplication factor, MLO as shown in the following equation: MLO=2LOMODE−1 (2) That is, divide by 2, or multiply by 1, 2, or 4. To ensure that the desired output signal downconverts at the desired IF output frequency, fIF, the frequency supplied to the LO interface must meet the following condition: fLO= fRF±fIF/MLO (3) Note, as previously detailed in Table 1, that the divide-by-2 mode can only be used for LO input frequencies up to 2.4 GHz, whereas the doubler and quadrupler modes only operate from 2 GHz to 8 GHz and from 4 GHz to 8 GHz, respectively. The LO interface also contains high-frequency filters that suppress the harmonics and subharmonics in the multiplier outputs. The center frequency of these filters can be programmed through Register 0x21 and Register 0x22. OFFSET FREQUENCY INTERFACE Further simplification of the VNA configuration can be achieved by employing the differential offset frequency interface. In this configuration, a single swept source can be used to drive the RF and LO interfaces at the same frequency (zero frequency offset), while the IF output frequency is set by the signal applied to the offset frequency interface. To enable the offset mixer, clear Bit 4 in Register 0x20 and program the OFMODE bits in Bits[3:2] in Register 0x20. The offset frequency input interface, when enabled, contains a programmable divider with ratios of 1, 2, or 4. The multiplication factor, MOF, is as shown in Table 7. Table 7. Offset Input Configuration Register 0x20, BIts[3:2], OFMODE Divide by MOF 00 1 1 01 2 0.5 10 (Default) 4 0.25 11 Dividers off Not applicable The IF output signal frequency, including the offset mixer, is repre- sented as follows: fIF=fRF−MLO×fLO+MOF×fOF (4) For a true zero-offset sweep, the LO frequency, therefore, must satisfy the following: fLO=fRF/MLO (5) such that the first two terms of Equation 4 cancel out, and the IF output frequency equals the following: fIF=MOF×fOF (6) The MOF = 1/4 (OFMODE = 2) setting is particularly useful and is the recommended OFMODE setting. When the offset frequency interface is driven by the ADC sample clock frequency, fS, it centers precisely the IF output signal in the first Nyquist zone of the ADC, with 4× domain sample points per completed cycle of the IF waveform. In this mode, the discrete time nature of the IF waveform becomes evident due to the divide by 4 digital dividing of the offset input. IF SIGNAL PATH The IF output signal of the mixers is passed through LPFs to remove unwanted mixing products and noise. The bandwidth of these filters is SPI-programmable through Register 0x25. The same bandwidth setting is applied to both ADL5961 IF channels. The IF amplifiers that follow the LPFs have individually SPI-pro- grammable gain, adjustable in 6 dB steps. This programmable gain enables optimal interfacing of both channels to the ADC input dynamic range. The IF output interfaces of the ADL5961 are suited to drive a wide range of ADCs directly. To avoid aliasing of broadband noise, it is recommended to insert a simple antialiasing filter as shown in Figure 53. Figure 53. Interfacing the ADL5961 to an ADC Each of the differential IF output nodes are low source impedance. For this reason, it is recommended to use series resistors when necessary, such as for driving filters or highly capacitive loads or cables, as shown on the test circuit (see Figure 72). |
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