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ADL5961ACCZ-R2 数据表(PDF) 6 Page - Analog Devices

部件名 ADL5961ACCZ-R2
功能描述  9 kHz to 26.5 GHz Integrated Vector Network Analyzer Front End
PDF  34 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL5961ACCZ-R2 数据表(HTML) 6 Page - Analog Devices

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Data Sheet
ADL5961
SPECIFICATIONS
analog.com
Rev. 0 | 6 of 34
Table 2. SPI Timing Specifications (Continued)
Parameter
Description
Min
Typ
Max
Unit
tZ
Maximum time delay between CS deactivation and SDIO bus return to
high impedance
150
ns
tACCESS
Maximum time delay between falling edge of SCLK and output data
valid for a read operation
30
ns



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