PPC440SP-RNC533C datasheet(5/85 Pages) AMCC

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PowerPC 440SP Embedded Processor

Revision 1.23 - Sept 26, 2006

AMCC Proprietary

Data Sheet

PPC440SP Functional Block Diagram

Figure 2. PPC440SP Functional Block Diagram

The PPC440SP is a System on a chip, which uses IBM® CoreConnect Bus™ Architecture.

Implemented with the Crossbar option, the IBM CoreConnect buses provide:

• 128-bit Data, 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data

paths (10.6GB/sec total)

• 32-bit OPB interfaces up to 83.33MHz, 333MB/s

Address Maps

The PPC440SP incorporates two address maps. The first is a fixed processor system memory address map. This

address map defines the possible contents of various processor accessible address regions. The second address

map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the

PPC440SP processor through the use of mtdcr and mfdcr instructions.

UART2

UART1

IIC1

Processor Core

DCR Bus

32KB

On-chip Peripheral Bus (OPB)

GPIO

Accelerator

Bridge

DDR2 SDRAM

External

Bus Controller

Controller

Clock,

Control,

Reset

Power

Mgmt

JTAG

Timers

MMU

Unit

OPB

Interrupt

Controller

Universal

I-Cache

32KB

D-Cache

XOR/DMA

PPC440

DDR PCI-X

MAL

Ethernet

DCRs

GPT

L2 Cache/SRAM

10/100/

Low Latency (LL) Segment

High Bandwidth (HB) Segment

Controller

Processor Local Bus (PLB)

Trace

Arbiter

PLB

I2O/DMA

Host

Local

64 bits

Local

32 bits

Memory

PCI0

PCI1

PCI2

1000

MII,

GMII

(EBC)

(DMA0 and

DMA1)

(DMA2)

Queue

IIC0

UART0

(EMAC)

PPC440SP-RNC533C 数据表(PDF) 5 Page - Applied Micro Circuits Corporation

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