PPC440SP-RNC533C datasheet(81/85 Pages) AMCC

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PowerPC 440SP Embedded Processor

Revision 1.23 - Sept 26, 2006

AMCC Proprietary

Data Sheet

Figure 10 shows the data strobe (DQS) and the data to be coincident. There is actually a slight skew as specified

by the SDRAM specifications, and there can be additional skew due to loading and signal routing. It is

recommended that the signal length for all of the eight DQS signals be matched.

Figure 10. DDR SDRAM Memory Data and DQS

Table 20. DDR SDRAM I/O Read Timing—TSD and THD

Notes:

1. TSD and THD are measured under worst case conditions.

2. Clock speed for the values in the table is 333.33MHz.

3. The time values in the table include 1/4 of a cycle at 166MHz (3ns x 0.25 = 0.75 ns).

4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4

of the cycle time for the lower clock frequency (e.g., TSD - 0.75 + 0.25TCYC).

Signal Names

Reference Signal

Read Data vs DQS Setup

TSD (ns)

Read Data vs DQS Hold

THD (ns)

MemData00:07

DQS0

0.00

1.00

MemData08:15

DQS1

0.00

1.00

MemData16:23

DQS2

0.00

1.00

MemData24:31

DQS3

0.00

1.00

MemData32:39

DQS4

0.00

1.00

MemData40:47

DQS5

0.00

1.00

MemData48:55

DQS6

0.00

1.00

MemData56:63

DQS7

0.00

1.00

ECC0:7

DQS8

0.00

1.00

DQS

MemData

TSD

THD

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