PPC440SP-RNC533C datasheet(61/85 Pages) AMCC

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PowerPC 440SP Embedded Processor

Revision 1.23 - Sept 26, 2006

AMCC Proprietary

Data Sheet

System Interface

Halt

Halt from external debugger.

3.3V LVTTL

1, 4

GPIO00:17

General purpose I/O 0 through 17. To access these

functions, software must set DCR register bits.

I/O

3.3V LVTTL

GPIO18:29

General purpose I/O 18 through 29. To access these

functions, software must set DCR register bits.

I/O

3.3V PCI

GPIO30:31

General purpose I/O 30 through 31. To access these

functions, software must set DCR register bits.

I/O

3.3V LVTTL

SysClk

Main system clock input.

3.3V LVTTL

SysErr

Set to 1 when a machine check is generated.

3.3V LVTTL

SysPartSel

Not used.

SysReset

Main system reset. External logic can drive this

bidirectional pin low (minimum of 16 cycles) to initiate a

system reset. A system reset can also be initiated by

software.

3.3V LVTTL

1, 2

HISRRst

Hardware initiated self-refresh and system reset.

3.3V LVTTL

1, 2

ExtReset

External Reset. During the PPC440SP’s reset phase,

this signal is at down level.

O3.3V LVTTL

TestEn

Test Enable.

3.3V LVTTL

TmrClk

Processor timer external input clock.

3.3V LVTTL

JTAG Interface

TCK

Test Clock.

3.3V LVTTL

TDI

Test Data In.

3.3V LVTTL w/pull-down

TDO

Test Data Out.

3.3V LVTTL

TMS

Test Mode Select.

3.3V LVTTL with pull-up

TRST

Test Reset. During chip power-up, this signal must be

low from the start of VDD ramp-up until at least 16

SysClk cycles after VDD is stable in order to initialize the

JTAG controller.

3.3V LVTTL with pull-up

Trace Interface

TrcClk

Trace data capture clock, runs at 1/4 the frequency of

the processor.

O3.3V LVTTL

TrcBS0:2

Trace branch execution status.

3.3V LVTTL

TrcES0:4

Trace Execution Status is presented every fourth

processor clock cycle.

O3.3V LVTTL

TrcTS0:6

Additional information on trace execution and branch

status.

O3.3V LVTTL

Table 6. Signal Functional Description (Sheet 6 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PPC440SP-RNC533C 数据表(PDF) 61 Page - Applied Micro Circuits Corporation

PPC440SP-RNC533C 数据表(HTML) 61 Page - Applied Micro Circuits Corporation

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PPC440SP-RNC533C 数据表(PDF) 61 Page - Applied Micro Circuits Corporation

PPC440SP-RNC533C 数据表(HTML) 61 Page - Applied Micro Circuits Corporation

Html Pages

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