ADP1829ACPZ-R7 datasheet(13/32 Pages) AD

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ADP1829

Rev. 0 | Page 13 of 32

THEORY OF OPERATION

The ADP1829 is a dual, synchronous, PWM buck controller

capable of generating output voltages down to 0.6 V and output

currents in the tens of amps. The switching of the regulators is

interleaved for reduced current ripple. It is ideal for a wide

range of applications, such as DSP and processor core I/O

supplies, general-purpose power in telecommunications,

medical imaging, gaming, PCs, set-top boxes, and industrial

controls. The ADP1829 controller operates directly from 3.0 V

to 18 V, and the power stage input voltage range is 1 V to 24 V,

which applies directly to the drain of the high-side external

power MOSFET. It includes fully integrated MOSFET gate

drivers and a linear regulator for internal and gate drive bias.

The ADP1829 operates at a fixed 300 kHz or 600 kHz switching

frequency. The ADP1829 can also be synchronized to an

external clock to switch at up to 1 MHz per channel. The

ADP1829 includes soft start to prevent inrush current during

startup, as well as a unique adjustable lossless current limit.

The ADP1829 offers flexible tracking for startup and shutdown

sequencing. It is specified over the −40°C to +85°C temperature

range and is available in a space-saving, 5 mm × 5 mm,

32-lead LFCSP.

INPUT POWER

The ADP1829 is powered from the IN pin up to 18 V. The

internal low dropout linear regulator, VREG, regulates the IN

voltage down to 5 V. The control circuits, gate drivers, and

external boost capacitors operate from the LDO output. Tie the

PV pin to VREG and bypass VREG with a 1 μF or greater

capacitor.

The ADP1829 phase shifts the switching of the two step-down

converters by 180°, thereby reducing the input ripple current.

This reduces the size and cost of the input capacitors. The input

voltage should be bypassed with a capacitor close to the high-

side switch MOSFETs (see the Selecting the Input Capacitor

section). In addition, a minimum 0.1 μF ceramic capacitor

should be placed as close as possible to the IN pin.

The VREG output is sensed by the undervoltage lockout

(UVLO) circuit to be certain that enough voltage headroom

is available to run the controllers and gate drivers. As VREG

rises above about 2.7 V, the controllers are enabled. The IN

voltage is not directly monitored by UVLO. If the IN voltage is

insufficient to allow VREG to be above the UVLO threshold,

the controllers are disabled but the LDO continues to operate.

The LDO is enabled whenever either EN1 or EN2 is high, even

if VREG is below the UVLO threshold.

If the desired input voltage is between 3.0 V and 5.5 V, connect

the IN directly to the VREG and PV pins, and drive LDOSD

high to disable the internal regulator. The ADP1829 requires

that the voltage at VREG and PV be limited to no more than

5.5 V. This is the only application where the LDOSD pin is used,

and it should otherwise be grounded or left open. LDOSD has

an internal 100 kΩ pull-down resistor.

While IN is limited to 18 V, the switching stage can run from up

to 24 V and the BST pins can go to 30 V to support the gate drive.

This can provide an advantage, for example, in the case of high

frequency operation from a high input voltage. Dissipation on the

ADP1829 can be limited by running IN from a low voltage rail

while operating the switches from the high voltage rail.

START-UP LOGIC

The ADP1829 features independent enable inputs for each

channel. Drive EN1 or EN2 high to enable their respective

controllers. The LDO starts when either channel is enabled.

When both controllers are disabled, the LDO is disabled and

the IN quiescent current drops to about 10 μA. For automatic

startup, connect EN1 and/or EN2 to IN. The enable pins are

18 V compliant, but they sink current through an internal

100 kΩ resistor once the EN pin voltage exceeds about 5 V.

INTERNAL LINEAR REGULATOR

The internal linear regulator, VREG, is low dropout, meaning it

can regulate its output voltage close to the input voltage. It

powers up the internal control and provides bias for the gate

drivers. It is guaranteed to have more than 100 mA of output

current capability, which is sufficient to handle the gate drive

requirements of typical logic threshold MOSFETs driven at up

to 1 MHz. Bypass VREG with a 1 μF or greater capacitor.

Because the LDO supplies the gate drive current, the output of

VREG is subjected to sharp transient currents as the drivers

switch and the boost capacitors recharge during each switching

cycle. The LDO has been optimized to handle these transients

without overload faults. Due to the gate drive loading, using the

VREG output for other auxiliary system loads is not

recommended.

The LDO includes a current limit well above the expected

maximum gate drive load. This current limit also includes a

short-circuit foldback to further limit the VREG current in the

event of a fault.

OSCILLATOR AND SYNCHRONIZATION

The ADP1829 internal oscillator can be set to either 300 kHz or

600 kHz. Drive the FREQ pin low for 300 kHz; drive it high for

600 kHz. The oscillator generates a start clock for each

switching phase and also generates the internal ramp voltages

for the PWM modulation.

The SYNC input is used to synchronize the converter switching

frequency to an external signal. The SYNC input should be

driven with twice the desired switching frequency because the

SYNC input is divided by 2 and the resulting phases are used to

clock the two channels alternately.

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