ADP1829ACPZ-R7 datasheet(20/32 Pages) AD

20 / 32 page

ADP1829

Rev. 0 | Page 20 of 32

The rest of the system gain is needed to reach 0 dB at crossover.

The total gain of the system, therefore, is given by

AT = AMOD + AFILTER + ACOMP

(26)

where:

AMOD is the gain of the PWM modulator.

AFILTER is the gain of the LC filter including the effects of

the ESR zero.

ACOMP is the gain of the compensated error amplifier.

Additionally, the phase of the system must be brought back up

to guarantee stability. Note from the bode plot of the filter that

the LC contributes −180° of phase shift. Additionally, because

the error amplifier is an integrator at low frequency, it contrib-

utes an initial −90°. Therefore, before adding compensation or

accounting for the ESR zero, the system is already down −270°.

To avoid loop inversion at crossover, or −180° phase shift, a

good initial practical design is to require a phase margin of 60°,

which is therefore an overall phase loss of −120° from the initial

low frequency dc phase. The goal of the compensation is to

boost the phase back up from −270° to −120° at crossover.

The two common compensation schemes used are sometimes

referred to as Type II or Type III compensation, depending on

whether the compensation design includes two or three poles.

(Dominant-pole compensations, or single-pole compensation,

is referred to as Type I compensation, but unfortunately, it is not

very useful for dealing successfully with switching regulators.)

If the zero produced by the ESR of the output capacitor provides

sufficient phase boost at crossover, Type II compensation is

adequate. If the phase boost produced by the ESR of the output

capacitor is not sufficient, another zero is added to the

compensation network, and thus, Type III is used.

In Figure 27, the location of the ESR zero corner frequency

gives significantly different net phase at the crossover frequency.

Use the following guidelines for selecting between Type II and

Type III compensators:

ESRZ

≤

, use Type II compensation.

ESRZ

, use Type III compensation.

GAIN

FREQUENCY

PHASE

LC FILTER BODE PLOT

PHASE CONTRIBUTION AT CROSSOVER

OF VARIOUS ESR ZERO CORNERS

fSW

fCO

fESR3

fESR2

fESR1

0dB

fLC

–40dB/dec

–20dB/dec

0°

–90°

–180°

Φ1

Φ2

Φ3

Figure 27. LC Filter Bode Plot

The following equations were used for the calculation of the

compensation components as shown in Figure 28 and Figure 29:

(27)

)

(

TOP

(28)

(29)

(30)

where:

fZ1 is the zero produced in the Type II compensation.

fZ2 is the zero produced in the Type III compensation.

fP1 is the pole produced in the Type II compensation.

fP2 in the pole produced in the Type III compensation.

ADP1829ACPZ-R7 数据表(PDF) 20 Page - Analog Devices

ADP1829ACPZ-R7 数据表(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表下载