ADP1829ACPZ-R7 datasheet(23/32 Pages) AD

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ADP1829

Rev. 0 | Page 23 of 32

COINCIDENT TRACKING

The most common application is coincident tracking, used in

core vs. I/O voltage sequencing and similar applications.

Coincident tracking limits the slave output voltage to be the

same as the master voltage until it reaches regulation. Connect

the slave TRK input to a resistor divider from the master voltage

that is the same as the divider used on the slave FB pin. This

forces the slave voltage to be the same as the master voltage.

For coincident tracking, use RTRKT = RTOP and RTRKB = RBOT,

where RTOP and RBOT are the values chosen in the Compensating

the Voltage Mode Buck Regulator section.

TIME

SLAVE VOLTAGE

MASTER VOLTAGE

Figure 31. Coincident Tracking

As the master voltage rises, the slave voltage rises identically.

Eventually, the slave voltage reaches its regulation voltage,

where the internal reference takes over the regulation while the

TRK input continues to increase and thus removes itself from

influencing the output voltage. To ensure that the output voltage

accuracy is not compromised by the TRK pin being too close in

voltage to the 0.6 V reference, make sure that the final value of

the master voltage is greater than the slave regulation voltage by

at least 10%, or 60 mV, as seen at the FB node, and the higher,

the better. A difference of 60 mV between TRK and the 0.6 V

reference produces about 3 mV of offset in the error amplifier,

or 0.5%, at room temperature, while 100 mV between them

produces only 0.6 mV or 0.1% offset.

RATIOMETRIC TRACKING

Ratiometric tracking limits the output voltage to a fraction of

the master voltage. For example, the termination voltage for

DDR memories, VTT, is set to half the VDD voltage.

TIME

SLAVE VOLTAGE

MASTER VOLTAGE

Figure 32. Ratiometric Tracking

For ratiometric tracking, the simplest configuration is to tie the

TRK pin of the slave channel to the FB pin of the master channel.

This has the advantage of having the fewest components, but

the accuracy suffers as the TRK pin voltage becomes equal to

the internal reference voltage and an offset is imposed on the

error amplifier of about −18 mV at room temperature.

A more accurate solution is to provide a divider from the

master voltage that sets the TRK pin voltage to be something

lower than 0.6 V at regulation, for example, 0.5 V. The slave

channel can be viewed as having a 0.5 V external reference

supplied by the master voltage.

Once this is complete, the FB divider for the slave voltage is

designed as in the Compensating the Voltage Mode Buck

Regulator section, except to substitute the 0.5 V reference for

the VFB voltage. The ratio of the slave output voltage to the

master voltage is a function of the two dividers.

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

TRKB

TRKT

BOT

TOP

MASTER

OUT

(52)

Another option is to add another tap to the divider for the

master voltage. Split the RBOT resistor of the master voltage into

two pieces, with the new tap at 0.5 V when the master voltage is

in regulation. This saves one resistor, but be aware that Type III

compensation on the master voltage causes the feedforward

signal of the master voltage to appear at the TRK input of the

slave channel.

By selecting the resistor values in the divider carefully, Equation 52

shows that the slave voltage output can be made to have a faster

ramp rate than that of the master voltage by setting the TRK

voltage at the slave larger than 0.6 V and RTRKB greater than

RTRKT. Make sure that the master SS period is long enough (that

is, sufficiently large SS capacitor) such that the input inrush

current does not run into the current limit of the power supply

during startup.

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