ADP1829ACPZ-R7 datasheet(18/32 Pages) AD

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ADP1829

Rev. 0 | Page 18 of 32

SETTING THE CURRENT LIMIT

The current-limit comparator measures the voltage across the

low-side MOSFET to determine the load current.

The current limit is set through the current-limit resistor, RCL.

The current sense pins, CSL1 and CSL2, source 50 μA through

their respective RCL. This creates an offset voltage of RCL multiplied

by the 50 μA CSL current. When the drop across the low-side

MOSFET RDSON is equal to or greater than this offset voltage, the

ADP1829 flags a current-limit event.

Because the CSL current and the MOSFET RDSON vary over

process and temperature, the minimum current limit should be

set to ensure that the system can handle the maximum desired

load current. To do this, use the peak current in the inductor,

which is the desired current-limit level plus the ripple current,

the maximum RDSON of the MOSFET at its highest expected

temperature, and the minimum CSL current.

μA

)

(MAX

DSON

LPK

(15)

where

ILPK is the peak inductor current.

In addition, the ADP1829 offers a technique for implementing

a current-limit foldback in the event of a short circuit with the

use of an additional resistor, as shown in Figure 25. Resistor RLO

is largely responsible for setting the foldback current limit during

a short circuit, and RHI is mainly responsible for setting up the

normal current limit. RLO is lower than RHI. These current-limit

sense resistors can be calculated by

μA

)

(

MAX

DSON

PKFOLDBACK

(16)

μA

)

(

−

MAX

DSON

LPK

OUT

(17)

where:

IPKFOLDBACK is the desired short circuit peak inductor current limit.

ILPK is the peak inductor current limit during normal operation

and is also used in Equation 15.

ADP1829

CSL

VIN

RLO

RHI

COUT

VOUT

Figure 25. Short Circuit Current Foldback Scheme

Because the buck converters are usually running fairly high

current, PCB layout and component placement may affect the

current-limit setting. An iteration of the RCL or RLO and RHI

values may be required for a particular board layout and

MOSFET selection. If alternate MOSFETs are substituted at

some point in production, these resistor values may also need

an iteration.

FEEDBACK VOLTAGE DIVIDER

The output regulation voltage is set through the feedback

voltage divider. The output voltage is reduced through the

voltage divider and drives the FB feedback input. The regulation

threshold at FB is 0.6 V. The maximum input bias current into

FB is 100 nA. For a 0.15% degradation in regulation voltage and

with 100 nA bias current, the low-side resistor, RBOT, needs to be

less than 9 kΩ, which results in 67 μA of divider current. For

RBOT, use 1 kΩ to 10 kΩ. A larger value resistor can be used, but

would result in a reduction in output voltage accuracy due to

the input bias current at the FB pin, while lower values cause

increased quiescent current consumption. Choose RTOP to set

the output voltage by using the following equation:

⎟

⎠

⎞

⎜

⎝

⎛

−

OUT

BOT

TOP

(18)

where:

RTOP is the high-side voltage divider resistance.

RBOT is the low-side voltage divider resistance.

VOUT is the regulated output voltage.

VFB is the feedback regulation threshold, 0.6 V.

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