5

 2006 Semtech Corp.

www.semtech.com

SC1486A

POWER MANAGEMENT

Notes:

(1) The output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the

ripple voltage.

(2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the

low-side MOSFET. These values guaranteed by the ILIM Source Current and Current Comparator Offset tests.

(3) clks = switching cycles.

(4) Guaranteed by design. See Shoot-Through Delay Timing Diagram below.

(5) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7.

(6) This device is ESD sensitive. Use of standard ESD handling precautions is required.

Electrical Characteristics (Cont.)

r

e

t

e

m

a

r

a

Ps

n

o

i

t

i

d

n

o

CC

°

5

2C

°

5

2

1

o

t

C

°

0

4

-s

t

i

n

U

n

i

Mp

y

Tx

a

Mn

i

Mx

a

M

s

r

e

v

i

r

D

e

t

a

G

y

a

l

e

D

h

g

u

o

r

h

T

-

t

o

o

h

S

)

4

(

g

n

i

s

ir

L

D

r

o

H

D0

3s

n

e

c

n

a

t

s

i

s

e

R

n

w

o

D

-l

l

u

P

L

Dw

o

l

L

D8

.

06

.

1

Ω

t

n

e

r

r

u

C

k

n

i

S

L

DV

5

.

2

=

L

D1

.

3

Α

e

c

n

a

t

s

i

s

e

R

p

U

-l

l

u

P

L

Dh

g

i

h

L

D2

4

Ω

t

n

e

r

r

u

C

e

c

r

u

o

S

L

DV

5

.

2

=

L

D3

.

1A

e

c

n

a

t

s

i

s

e

R

n

w

o

D

-l

l

u

P

H

DV

5

=

X

L

-

T

S

B

,

w

o

l

H

D2

4

Ω

e

c

n

a

t

s

i

s

e

R

p

U

-l

l

u

P

H

DV

5

=

X

L

-

T

S

B

,

h

g

i

h

H

D2

4

Ω

t

n

e

r

r

u

C

e

c

r

u

o

S

/

k

n

i

S

H

DV

5

.

2

=

L

D3

.

1A

Test Conditions: V

Shoot-Through Delay Timing Diagram

tplhDL

tplhDH

LX

DL

DL

DH