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 2006 Semtech Corp.

www.semtech.com

SC1486A

POWER MANAGEMENT

Application Information (Cont.)

Layout Guidelines

One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and

maximize heat dissipation. The IC ground references, VSSA1 and VSSA2, should be kept separate from power

ground. All components that are referenced to them should connect to them locally at the chip. VSSA1 and VSSA2

should connect to power ground at their respective output capacitors only.

Feedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives.

Route feedback traces with their respective VSSAs as a differential pair from the output capacitor back to the chip.

Run them in a “quiet layer” if possible.

Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins and connected directly to them on the

same side.

Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling

(including the chip power ground connections). Power components should be placed to minimize loops and reduce

losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use

“minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of

the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical.

Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling

requirement (and to reduce parasitics) if routed on more than one layer

Current sense connections must always be made using Kelvin connections to ensure an accurate signal.

We will examine the SC1486A DDR2 reference design used in the Design Procedure section while explaining the

layout guidelines in more detail.

VSSA1

C11 0u1

C8

1u

0402

C16

0u1

0402

R2 10R

VCCA1

C2

0u1/25V

+

C15

220u/25m

+

C14

330u/25m

R13

17k4

C10 0u1

R8

0R

R10

45k3

0603

0603

C9

1u

0402

TON2

PGOOD2

R1 10R

C7

2n2/50V

R9 10k0

Q1

FDS6982S

4

1

2

3

5

6

7

8

U1

SC1486A

3

1

23

6

7

5

4

22

27

24

26

25

28

17

15

9

20

21

19

18

13

12

8

10

11

14

2

16

VDDP1

PGND1

TON1

DH1

BST1

LX1

ILIM1

EN/PSV1

PGD1

VOUT1

FB1

VCCA1

VSSA1

VDDP2

PGND2

TON2

DH2

BST2

LX2

ILIM2

PGD2

FB2

REFIN

REFOUT

VCCA2

VSSA2

DL1

DL2

R14 470k

R3

1M

7343

R6 4k32

0603

1210

0402

VCCA1

R7

0R

PWR_SRC

PGD2

TON1

0402

SOD

0402

R5 13k3

REFOUT

Q2

IRF7811AV

1

2

3

4

5

6

7

8

S

S

S

G

D

D

D

D

D2

0402

C19

0u1

C6

0u1/25V

323

PGOOD1

0402

0603

0.9V

0.9V, 1.5A

VCCA2

L2

3u9

R15 470k

0402

VCCA1

0402

0402

0603

C23

1n

C1

2n2/50V

0402

0603

VCCA2

0402

C20

1n

0402

1210

5VSUS

1.8V

0402

C12

0u1

0402

1.8V, 10A

C3

10u/25V

Q3

FDS6676S

1

2

3

4

5

6

7

8

S

S

S

G

D

D

D

D

VSSA2

0603

0603

0402

1.8V

SOD

0402

+

C13

330u/25m

7343

C22

1u

5VSUS

PGD1

PWR_SRC

C18

1u

0402

0402

L1

2u4

D1

R12

10k0

R4

649k

0402

7343

323

C21

1u

0402

C17

27p

0603

0402

R11 10R

1210

C4

10u/25V

5VRUN

C5

10u/25V

Figure 4: DDR2 Reference Design and Layout Example

Sample DDR2 Design Using SC1486A

PWR_SRC = 7.5V to 20.5V

VDDQ = 1.8V @ 10A

VTT = 0.9V @ 1.5A

Schematic is drawn to emphasize required grounding scheme