SC1486AEVB datasheet(11/30 Pages) SEMTECH

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 2006 Semtech Corp.

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SC1486A

POWER MANAGEMENT

Application Information (Cont.)

Current Limit Circuit (Cont.)

latches off due to output overvoltage (see Output

Overvoltage Protection).

Power Good Output

Each controller has its own power good output. Power

good is an open-drain output and requires a pull-up

resistor. When VDDQ is 10% above or below its set volt-

age, or VTT is 2V or 10% below REFOUT, PGD for that

output gets pulled low. It is held low until the output volt-

age returns to within these limits. PGD is also held low

during start-up and will not be allowed to transition high

until soft start is over (440 switching cycles) and the out-

put reaches 90% of its set voltage. There is a 5µs delay

built into the PGD circuitry to prevent false transitions.

Output Overvoltage Protection

When VDDQ exceeds 10% of its set voltage or VTT

exceeds 2V, the low side MOSFET for that output is

latched on. It stays latched on and the controller is latched

off until reset (see below). There is a 5µs delay built into

the OV protection circuit to prevent false transitions. An

OV fault in VTT will not affect VDDQ. An OV fault in VDDQ

will shut down VTT if VDDQ is used to generate REFIN.

Note: to reset VDDQ from any fault, VCCA1 or EN/PSV1

must be toggled. To reset VTT from a fault, VCCA2 or

REFIN must be toggled.

Output Undervoltage Protection

When the output is 30% (20% for VTT) below its set volt-

age the output is latched in a tri-stated condition. It stays

latched and the controller is latched off until reset (see

below). There is a 5µs delay built into the UV protection

circuit to prevent false transitions. A UV fault in VTT will

not affect VDDQ. A UV fault in VDDQ will shut down VTT if

VDDQ is used to generate REFIN. Note: to reset VDDQ

from any fault, VCCA1 or EN/PSV1 must be toggled. To

reset VTT from a fault, VCCA2 or REFIN must be toggled.

POR, UVLO and Softstart

An internal power-on reset (POR) occurs when VCCA1 and

VCCA2 exceed 3V, resetting the fault latch and soft-start

counter, and preparing the PWM for switching. VCCA

undervoltage lockout (UVLO) circuitry inhibits switching

and forces the DL gate driver high until VCCA rises above

4.2V. At this time the circuit will come out of UVLO and

begin switching, and with the softstart circuit enabled,

will progressively limit the output current (by limiting the

current out of the ILIM pin) over a predetermined time

period of 440 switching cycles. The VTT switcher

operates slightly differently in order to implement

Suspend to RAM (S3) mode. VDDP2 is used to enable

the switcher. If REFIN is greater than ~0.5V and VDDP2

is less than ~3.25V, REFOUT will be present but the VTT

switcher will be disabled (VTT = high-Z). If REFIN is greater

than ~0.5V and VDDP2 is greater than ~3.25V both

REFOUT and the VTT switcher will be enabled.

The ramp occurs in four steps:

1) 110 cycles at 25% ILIM with double minimum off-time

(for purposes of the on-time one-shot there is an

internal positive offset of 120mV to VOUT during this

period to aid in startup)

2) 110 cycles at 50% ILIM with normal minimum off-time

3) 110 cycles at 75% ILIM with normal minimum off-time

4) 110 cycles at 100% ILIM with normal minimum

off-time. At this point the output undervoltage and power

good circuitry is enabled.

There is 100mV of hysteresis built into the UVLO circuit

and when VCCA falls to 4.1V (nom.) the output drivers

are shut down and tristated.

MOSFET Gate Drivers

The DH and DL drivers are optimized for driving

moderate-sized high-side, and larger low-side power

MOSFETs. An adaptive dead-time circuit monitors the DL

output and prevents the high-side MOSFET from turning

on until DL is fully off (below ~1V). Conversely, it

monitors the phase node, LX, to determine the state of

the high side MOSFET, and prevents the low-side MOSFET

from turning on until DH is fully off (LX below ~1V). Be

sure there is low resistance and low inductance between

the DH and DL outputs to the gate of each MOSFET.

DDR Reference Buffer

The reference buffer is capable of driving 3mA and sinking

25µA. Since the output is class A, if additional sinking is

required an external pulldown resistor can be added.

Make sure that the ground side of this pulldown is tied

to VSSA2. As with most opamps, a small resistor is

required when driving a capacitive load. To ensure stability

use either a 10

Ω resistor in series with a 1µF capacitor

or a 100

Ω resistor in series with a 0.1µF capacitor from

REFOUT to AGND2.

Since it is possible to have as much as 10µF to 20µF of

capacitance at the memory socket or on-board the

DIMMs, it is recommended that a 0

Ω resistor is placed

between REFOUT and the DIMM sockets. This allows the

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