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SC1486A

POWER MANAGEMENT

Layout Guidelines (Cont.)

Key points for the power section:

1) there should be a very small input loop, well decoupled.

2) the phase node should be a large copper pour, but compact since this is the noisiest node.

3) input power ground and output power ground should not connect directly, but through the ground planes instead.

4) The two outputs should not share their input capacitors, and these should have separate PWR_SRC and PGND

(component-side) copper pours.

5) The two output inductors should not be placed adjacent to each other to avoid crosstalk.

6) Notice in Figures 10 and 11 on the previous page placement of 0

Ω resistor at the bottom of the output capacitor

to connect to VSSA1/2 for each output.

Connecting the control and power sections should be accomplished as follows (see Figure 16 below):

1) Route VSSA1/2 and their related feedback traces as differential pairs routed in a “quiet” layer away from noise

sources.

2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces

with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization,

with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power

ground as its return path. LX is the noisiest node in the circuit, switching between PWR_SRC and ground at high

frequencies, thus should be kept as short as practical. DH has LX as its return path.

3) BST is also a noisy node and should be kept as short as possible.

4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the

ground plane.

Q3

FDS6676S

1

2

3

4

5

6

7

8

S

S

S

G

D

D

D

D

U1

SC1486A

3

1

23

6

7

5

4

22

27

24

26

25

28

17

15

9

20

21

19

18

13

12

8

10

11

14

2

16

VDDP1

PGND1

TON1

DH1

BST1

LX1

ILIM1

EN/PSV1

PGD1

VOUT1

FB1

VCCA1

VSSA1

VDDP2

PGND2

TON2

DH2

BST2

LX2

ILIM2

PGD2

FB2

REFIN

REFOUT

VCCA2

VSSA2

DL1

DL2

PHASE NODES (BLACK) TO BE COPPER ISLANDS (PREFERRED) OR WIDE COPPER TR

GATE DRIVE TRACES (RED) AND PHASE NODE TRACES (BLUE) TO BE WIDE COPPER

TRACES (L:W < 20:1) AND AS SHORT AS POSSIBLE, WITH DL THE MOST CRITICAL

Q1

FDS6982S

4

1

2

3

5

6

7

8

L2

3u9

L1

2u4

Q2

IRF7811AV

1

2

3

4

5

6

7

8

S

S

S

G

D

D

D

D

Figure 16: Connecting Control and Power Sections

Application Information (Cont.)