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SC1486AEVB 数据表(PDF) 13 Page - Semtech Corporation |
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SC1486AEVB 数据表(HTML) 13 Page - Semtech Corporation |
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13 / 30 page ![]() 13 2006 Semtech Corp. www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) Design Procedure Prior to designing an output and making component selections, it is necessary to determine the input voltage range and the output voltage specifications. For purposes of demonstrating the procedure the VDDQ output for the schematic on page 17 will be designed. The maximum input voltage (V IN(MAX)) is determined by the highest AC adaptor voltage. The minimum input voltage (V IN(MIN)) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. For the purposes of this design example we will use a V IN range of 7.5V to 20.5V. Four parameters are needed for the output: 1) nominal output voltage, V OUT (for DDR2 this is 1.8V) 2) static (or DC) tolerance, TOL ST (for DDR2 this is +/-0.1V) 3) transient tolerance, TOL TR and size of transient (for DDR2 this is undefined, so assume +/-8% for purposes of this demonstration). 4) maximum output current, I OUT (we will design for 10A) Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. It is recommended that the two outputs are designed to operate at frequencies approximately 25% apart to avoid any possible interaction. It is also recommended that the higher frequency output is the lower output voltage output, since this will tend to have lower output ripple and tighter specifications. The default R tON values of 1MΩ and 649kΩ are suggested as a starting point, but these are not set in stone. The first thing to do is to calculate the on-time, t ON, at VIN(MIN) and V IN(MAX), since this depends only upon VIN, VOUT and R tON. For VOUT < 3.3V: () s 10 50 V V 10 37 R 10 3 . 3 t 9 ) MIN ( IN OUT 3 tON 12 ) MIN ( VIN _ ON − − • + • • + • • = and () s 10 50 V V 10 37 R 10 3 . 3 t 9 ) MAX ( IN OUT 3 tON 12 ) MAX ( VIN _ ON − − • + • • + • • = From these values of t ON we can calculate the nominal switching frequency as follows: () Hz t V V f ) MIN ( VIN _ ON ) MIN ( IN OUT ) MIN ( VIN _ SW • = and () Hz t V V f ) MAX ( VIN _ ON ) MAX ( IN OUT ) MAX ( VIN _ SW • = t ON is generated by a one-shot comparator that samples V IN via RtON, converting this to a current. This current is used to charge an internal 3.3pF capacitor to V OUT. The equations above reflect this along with any internal com- ponents or delays that influence t ON. For our DDR2 VDDQ example we select R tON = 1MΩ: t ON_VIN(MIN) = 871ns and tON_VIN(MAX) = 350ns f SW_VIN(MIN) = 275kHz and fSW_VIN(MAX) = 251kHz Now that we know t ON we can calculate suitable values for the inductor. To do this we select an acceptable inductor ripple current. The calculations below assume 50% of I OUT which will give us a starting place. () ()H I 5 . 0 t V V L OUT ) MIN ( VIN _ ON OUT ) MIN ( IN ) MIN ( VIN • • − = and () ()H I 5 . 0 t V V L OUT ) MAX ( VIN _ ON OUT ) MAX ( IN ) MAX ( VIN • • − = For our DDR2 VDDQ example: L VIN(MIN) = 1µH and LVIN(MAX) = 1.3µH We will select an inductor value of 2.4µH to reduce the ripple current, which can be calculated as follows: () P P ) MIN ( VIN _ ON OUT ) MIN ( IN ) MIN ( VIN _ RIPPLE A L t V V I − • − = and () P P ) MAX ( VIN _ ON OUT ) MAX ( IN ) MAX ( VIN _ RIPPLE A L t V V I − • − = |
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