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RT8800AGQV 数据表(PDF) 13 Page - Richtek Technology Corporation

部件名 RT8800AGQV
功能描述  General Purpose 3-Phase PWM Controller for High-Density Power Supply
PDF  21 Pages
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制造商  RICHTEK [Richtek Technology Corporation]
网页  http://www.richtek.com
标志 RICHTEK - Richtek Technology Corporation

RT8800AGQV 数据表(HTML) 13 Page - Richtek Technology Corporation

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RT8800A
13
DS8800A-04 August 2007
www.richtek.com
All brand name or trademark belong to their owner respectively
Figure 9
COMM
LX
ADJ
CORE
CORE
R
x
3
R
x
R
ΔI
ΔV
Line
Load
−
=
=
Dead Zone Elimination and Output Voltage Offset
Function
RT8800A samples and holds inductor valley current by
time-sharing sourcing a current IX to RCOMM. At light load
condition the inductor valley current and consequently the
voltage VX across the sensing capacitor may be negative.
A negative IX is required to correctly sense the negative
voltage. However, the RT8800ACANNOT provide a negative
IX and consequently cannot sense negative inductor
current. This results in dead zone of load line performance
as shown in Figure 10. Therefore a technique as shown in
Figure 11 is required to eliminate the dead zone of load
line at light load condition.
Figure 10
Figure 11
Referring to Figure 11, the Schottky diode provides a
constant voltage drop VF with enough bias current. IX is
expressed as:
COMM
LX
LX_Valley
CSN
LX
LX_Valley
F
X
R
R
I
R
R
I
V
I
×
+
×
+
=
To make sure RT8800A could sense the inductor current,
right hand side of Equation (1) should always be positive:
0
R
R
I
R
R
I
V
COMM
LX
LX_Valley
CSN
LX
LX_Valley
F
≥
×
+
×
+
Since VF >> (ILX_Valley x RLX) in practical application,
Equation (2) could be simplified as:
COMM
LX
LX_Valley
CSN
F
R
R
I
R
V
×
≥
(1)
(2)
(3)
Droop and Load Lind Setting
The sampled and held phase current IX are summed to get
sum(IX). RT8800A then sinks a current that is 1/3 sum(IX)
and produces a droop voltage that is proportional to the
average phase voltage.
VADJ = 1/3 sum(IX) x RADJ
VADJ is then subtracted form DAC generator output as the
real reference voltage at non-inverting input of the error
amplifier. Consequently, load line slope is calculated as:
+
-
0.8V
VREF
OVP
500mV
SUM/N
+
-
VID125
VID125
RT9401
VID [0 : 4]
VCORE
RADJ
PI
FB
COMP
IX
DAC_OUT
)
sum(I
3
1
X
VCORE
ICORE
DAC_OUT
VOFFSET
RCSN <
RCSN =
RCSN >
Load Line
Spec_High
Spec_Low
+
-
RCOMM
RCSN
DSKY
RCS
VCORE - VF
CX
+
VX
-
RX
LX
RL_X
IX
IL
VCORE



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