RT8800AGQV datasheet(16/21 Pages) RICHTEK

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RT8800A

DS8800A-04 August 2007

www.richtek.com

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Design Procedure Suggestion

a.Output filter pole and zero (Inductor, output capacitor

value & ESR).

b.Error amplifier compensation & sawtooth wave amp-

litude (compensation network).

Current Loop Setting

a.GM amplifier S/H current (current sense component

DCR, ICOMMON pin external resistor value).

b.Over-current protection trip point (RICOMMON1 resistor).

VRM Load Line Setting

a.Droop amplitude (PI pin resistor).

b.No load offset (RICOMMON2)

Power Sequence & SS

DVD pin external resistor and SS pin capacitor.

PCB Layout

a.Sense for current sense GM amplifier input.

b.Refer to layout guide for other items.

Voltage Loop Setting

Design Example

Given:

Apply for four phase converter

VIN = 12V

VCORE = 1.5V

ILOAD(MAX) = 100A

VDROOP = 100mV at full load (1m

Ω Load Line)

OCP trip point set at 35A for each channel (S/H)

DCR = 1m

Ω of inductor at 25°C

L = 1.5

μH

COUT = 8000

μF with 5mΩ equivalent ESR.

Figure 17. Type 2 compensation network of EA

2. Over-Current Protection Setting

Consider the temperature coefficient of copper

3900ppm/

°C,

RB2

RB1

15k

12nF

C2 68pF

4.7k

1. Compensation Setting

a. Modulator Gain, Pole and Zero:

From the following formula:

Modulator Gain =VIN/VRAMP =12/2.4=5 (i.e 14dB)

where VRAMP : ramp amplitude of saw-tooth wave

35.6A

150

330

1.39m

150

DCR

ICOMMON1

LC Filter Pole = 1.45kHz and

ESR Zero =3.98kHz

b. EA Compensation Network:

Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF

and use the Type 2 compensation scheme shown in

Figure 21. By calculation, the FZ = 0.88kHz,

FP = 322kHz and Middle Band Gain is 3.19 (i.e

10.07dB).

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