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KSZ9567R 数据表(PDF) 137 Page - Microchip Technology |
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KSZ9567R 数据表(HTML) 137 Page - Microchip Technology |
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137 / 233 page  2022 Microchip Technology Inc. and its subsidiaries DS00002329E-page 137 KSZ9567R 5.2.1.5 Port Interrupt Status Register These registers provide interrupt status for the individual ports. these interrupts are enabled in the Port Interrupt Mask Register. For non-port specific interrupt status, refer to the Global Interrupt Status Register. 5.2.1.6 Port Interrupt Mask Register This register enables the interrupts in the Port Interrupt Status Register. Address: 0xN01B Port N: 1-7 Size: 8 bits Bits Description Type Default 7:3 RESERVED RO 0000_00b 2 PTP Interrupt Status Applies only to PHY ports, not MAC port(s). Refer to the Port PTP Timestamp Interrupt Status Register for individual PTP interrupts. 0 = No interrupt 1 = Interrupt detected RO 0b 1 PHY Interrupt Status Applies only to PHY ports, not MAC port(s). Refer to the Port Interrupt Control / Status Register for individual PHY interrupts. 0 = No interrupt 1 = Interrupt detected RO 0b 0 ACL Interrupt Status ACL interrupts can be generated by configuring an entry in the ACL Table for counter mode. All ports have an ACL Table. To clear this bit, toggle the ACL Interrupt Mask bit in the Port Interrupt Mask Register. 0 = No interrupt 1 = Interrupt detected RO 0b Address: 0xN01F Port N: 1-7 Size: 8 bits Bits Description Type Default 7:3 RESERVED RO 0000_00b 2 PTP Interrupt Enable Applies only to PHY ports. Refer to the Port PTP Timestamp Interrupt Enable Register for individual PTP interrupt enables. 0 = Interrupt enabled 1 = Interrupt disabled R/W 0b 1 PHY Interrupt Enable Applies only to PHY ports. 0 = Interrupt enabled 1 = Interrupt disabled R/W 0b |
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