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KSZ9567R 数据表(PDF) 141 Page - Microchip Technology |
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KSZ9567R 数据表(HTML) 141 Page - Microchip Technology |
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141 / 233 page  2022 Microchip Technology Inc. and its subsidiaries DS00002329E-page 141 KSZ9567R Note 5-4 The default value of this field is determined by the associated configuration strap value. Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information. 5.2.2.2 PHY Basic Status Register PHY register 0x01. 7 Collision Test 1 = Enable COL test 0 = Disable COL test R/W 0b 6 Speed Select (MSB) This bit is ignored if auto-negotiation is enabled (bit 12 in this register). Bits [6, 13] 11 = Reserved 10 = 1000 Mb/s 01 = 100 Mb/s 00 = 10 Mb/s R/W Note 5-4 5:0 RESERVED RO 0x00 Address: 0xN102 - 0xN103 Port N: 1-5 Size: 16 bits Bits Description Type Default 15 100BASE-T4 0 = PHY is not 100BASE-T4 capable RO 0b 14 100BASE-TX Full Duplex 1 = PHY is 100BASE-TX full-duplex capable RO 1b 13 100BASE-TX Half Duplex 1 = PHY is 100BASE-TX half-duplex capable RO 1b 12 10 Mb/s Full Duplex 1 = PHY is 10 Mb/s full-duplex capable RO 1b 11 10 Mb/s Half Duplex 1 = PHY is 10 Mb/s half-duplex capable RO 1b 10:9 RESERVED RO 00b 8 Extended Status 1 = PHY Extended Status Register contains extended status information. RO 1b 7 RESERVED RO 0b 6 MF Preamble Suppression 1 = PHY will accept management frames with preamble suppressed RO 1b 5 Auto-negotiation Complete 1 = Auto-negotiation process is complete 0 = Auto-negotiation process is not complete RO - Bits Description Type Default |
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