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KSZ9567R 数据表(PDF) 171 Page - Microchip Technology

部件名 KSZ9567R
功能描述  7-Port Gigabit Ethernet Switch with Audio Video Bridging and Two RGMII/MII/RMII Interfaces
PDF  233 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

KSZ9567R 数据表(HTML) 171 Page - Microchip Technology

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DS00002329E-page 171
KSZ9567R
5.2.7.2
Port Priority Control Register
To achieve the desired functionality, do not set more than one bit at a time in this register.
5.2.7.3
Port Ingress MAC Control Register
Address:
0xN801
Port N: 1-7
Size:
8 bits
Bits
Description
Type
Default
7
Highest Priority
1 = Highest priority selected
0 = Highest priority not selected
R/W
0b
6
OR’ed Priority
1 = All available priority OR’ed
0 = All available priority not OR’ed
R/W
0b
5
RESERVED
RO
0b
4
MAC Address Priority Classification
1 = Enable MAC address priority classification for ingress packets on port
0 = Disable MAC address classification
R/W
0b
3
VLAN Priority Classification
1 = Enable VLAN priority classification for ingress packets on port
0 = Disabled VLAN classification
R/W
0b
2
802.1p Priority Classification
1 = Enable 802.1p priority classification for ingress packets on port
0 = Disable 802.1p priority classification
R/W
0b
1
Diffserv Priority Classification
1 = Enable Diffserv priority classification for ingress packets on port
0 = Disable Diffserv priority classification
R/W
0b
0
ACL Priority Classification
1 = Enable ACL priority classification for ingress packets on port
0 = Disable ACL priority classification
R/W
0b
Address:
0xN802
Port N: 1-7
Size:
8 bits
Bits
Description
Type
Default
7
User Priority Ceiling
1 = If a packet’s “user priority field” is greater than the “user priority field” in
the port default tag register, replace the packet’s user priority field with the
user priority field in the port default tag from the Port Default Tag 0 Register.
0 = Do not replace the user priority field at this port.
R/W
0b
6:5
RESERVED
RO
0b



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