KSZ9567R datasheet(225/233 Pages) MICROCHIP

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DS00002329E-page 225

KSZ9567R

APPENDIX A: DATA SHEET REVISION HISTORY

TABLE A-1:

REVISION HISTORY

Revision

Section/Figure/Entry

Correction

DS00002329E (07-15-22)

Section 5.1.4.72, "Global

PM Available Register"

The following has been defeatured in the docu-

ment: 'low latency cut through mode' and 'time

aware traffic scheduler per port'.

Table 3-2, "Pin Descriptions"

Updated Port Receive Error pin definition: from “MII

Mode” to “MII/RMII Modes” and “RMII/RGMII

Modes” to “RGMII Mode”.

Table 3.2.1, "Configuration

Straps"

Updated strapping pin high instructions from “a

non-LED pin” to “any pin”.

Table 3-3, "Configuration

Strap Descriptions"

Updated In-Band Management to include the fol-

lowing note: “If using I2C, do not enable IBA.”

Section 4.1.7, "Auto-Negoti-

ation"

Updated auto-negotiation bypass paragraph,

changing “operating mode” to “operating speed”.

Also added this sentence to the end of the para-

graph: “With parallel detection, the duplex will

always be half-duplex.”

Section 5.1.1.6, "Global

Interrupt Status Register"

Updated field 29:0 definition: from “Reserved” to

“APB Timeout Interrupt Status”.

Section 5.1.1.7, "Global

Interrupt Mask Register"

Updated field 29:0 definition: from “Reserved” to

“APB Timeout Interrupt Mask”.

Section 5.1.2.3, "In-Band

Management (IBA) Control

Updated bit 31 IBA Enable definition to add the fol-

lowing note: “If using I2C, do not enable IBA.”

Section 5.1.4.72, "Global

PM Available Register"

Added new register to accommodate Packet Mem-

ory Available Block Count.

Section 5.1.6.1, "Global PTP

Clock Control Register"

Added the following note to bit 1 definition: “The

PTP Clock must be enabled when using the time

stamp units (TSU) or trigger output units (TOU),

even if IEEEE 1588 is not implemented.”

Section 5.1.6.21, "Trigger

Output Unit Control 2 Regis-

ter"

Added the following note to the definition of bits 0-

31: “The minimum value for this parameter is

0x50.”

Section 5.1.6.24, "Trigger

Output Unit Control 5 Regis-

ter"

Removed the following sentence from the descrip-

tion of this register: “This register contains the PTP

event trigger output PPS signal pulse width for unit

2 and path delay compensation for

unit 1.”

Section 5.2.2.21, "Port Spe-

cial Register"

Added new register to accommodate Single-LED

Mode Workaround Bit.

Section 5.2.7.4, "Port

Authentication Control Reg-

ister"

Updated bit 2 Access Control List (ACL) Enable

definition from “0 = enable” to “0 = disable”.

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