KSZ9567R datasheet(147/233 Pages) MICROCHIP

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DS00002329E-page 147

KSZ9567R

5.2.2.10

PHY 1000BASE-T Control Register

PHY register 0x09.

Address:

0xN112 - 0xN113

Port N: 1-5

Size:

16 bits

Bits

Description

Type

Default

15:13

Test Mode Bits

[000] Normal operation

[001] Test mode 1 –Transmit waveform test

[010] Test mode 2 –Transmit jitter test in master mode

[011] Test mode 3 –Transmit jitter test in slave mode

[100] Test mode 4 –Transmitter distortion test

[101] Reserved, operations not identified

[110] Reserved, operations not identified

[111] Reserved, operations not identified

To enable 1000BASE-T Test Mode:

1) Set Register 0h = 0x0140 to disable auto-negotiation and select

1000Mbps speed.

2) Set Register 9h, bits [15:13] = 001, 010, 011, or 100 to select one of the

1000BASE-T Test Modes.

After the above settings, the test waveform for the selected test mode is

transmitted onto each of the 4 differential pairs. No link partner is needed.

R/W

000b

Master-Slave Manual Configuration Enable

1 = Enable master-slave manual configuration

0 = Disable master-slave manual configuration

R/W

Master-Slave Manual Configuration Value

This bit is ignored if master-slave manual configuration is disabled (bit 12)

1 = Configure PHY as master during master-slave negotiation

0 = Configure PHY as slave during master-slave negotiation

R/W

Port Type

This bit is valid only if master-slave manual configuration is disabled (bit 12)

1 = Indicate the preference to operate as multi-port device (master)

0 = Indicate the preference to operate as single-port device (slave)

R/W

1000BASE-T Full Duplex

1 = Advertise that PHY is 1000BASE-T full duplex capable

0 = Advertise that PHY is not 1000BASE-T full duplex capable

R/W

1000BASE-T Half Duplex

1 = Advertise that PHY is 1000BASE-T half duplex capable

0 = Advertise that PHY is not 1000BASE-T half duplex capable

R/W

7:0

RESERVED

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