L6740L datasheet(10/44 Pages) STMICROELECTRONICS

10 / 44 page

Pins description and connection diagrams

L6740L

10/44

CS4+

Channel 4 Current Sense Positive Input. Connect through an R-C filter

to the phase-side of the channel 4 inductor. When working at 2 or 3

phase, directly connect to Vout_CORE.

See Section 9 for proper layout of this connection.

CS4-

Channel 4 Current Sense Negative Input. Connect through a RG resis-

tor to the output-side of the channel inductor. When working at 2 or 3

phase, connect through RG to CS4+.

See Section 9 for proper layout of this connection.

OC_PHASE

Per-Phase Over Current (CORE Section).

Internally set to 1.24V, connecting to SGND with a resistor ROC_TH it

programs the OC threshold per-phase. See Section 7.4.1 for details.

Not internally connected.

NB_ISEN

NB Current Sense Pin.

Used for NB voltage positioning and NB_OCP. Connect through a resis-

tor RISEN to the relative LS Drain. See Section 7.4 for details.

Not internally connected.

25,

VID4, VID5

Voltage IDentification Pins.

Internally pulled-low by 10

µA, they are used to program the output

voltage. Used only in PVI-Mode, ignored when in SVI-Mode.See

Section 5 for details.

OSC / FLT

OSC: It allows programming the switching frequency FSW of both Sec-

tions. Switching frequency can be increased according to the resistor

ROSC connected from the pin to. SGND with a gain of 6.8kHz/µA (see

Section 8 for details). If floating, the switching frequency is 150kHz per

phase.

FLT: The pin is forced high (3.3V) in case of an OV / UV fault. To

recover from this condition, cycle VCC or the EN pin. See Section 7 for

details.

OC_AVG /

Average Over Current and Load Indicator Pin.

A current proportional to the current delivered by the CORE Section (a

copy of the DROOP current) is sourced through this pin.

The Average-OC threshold is programmed by connecting a resistor

ROC_AVG to SGND. When the generated voltage crosses the OC_AVG

threshold (VOC_AVGTH = 2.5V Typ) the device latches with all mosfets

OFF (to recover, cycle VCC or the EN pin).

A load indicator with 2.5V end-of-scale is then implemented.

See Section 7.4.1 for details.

NB_OS

Offset Programming Pin.

Internally set to 1.24V, connecting a ROS_NB resistor to SGND allows

setting a current that is mirrored into NB_FB pin in order to program a

positive offset according to the selected RFB_NB. Short to SGND to dis-

able the function. See Section 6.7 for details.

NB_FBG

Remote Ground Sense.

Connect to the negative side of the load to perform remote sense. See

Section 9 for proper layout of this connection.

Table 2.

Pin description (continued)

Pin#

Name

Function

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