L6740L datasheet(41/44 Pages) STMICROELECTRONICS

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L6740L

Layout guidelines

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Layout guidelines

Layout is one of the most important things to consider when designing high current

applications. A good layout solution can generate a benefit in lowering power dissipation on

the power paths, reducing radiation and a proper connection between signal and power

ground can optimize the performance of the control loops.

Two kind of critical components and connections have to be considered when laying-out a

VRM based on L6740L: power components and connections and small signal components

connections.

11.1

Power components and connections

These are the components and connections where switching and high continuous current

flows from the input to the load. The first priority when placing components has to be

reserved to this power section, minimizing the length of each connection and loop as much

as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections

must be a part of a power plane and anyway realized by wide and thick copper traces: loop

must be anyway minimized. The critical components, i.e. the power transistors, must be

close one to the other. The use of multi-layer printed circuit board is recommended.

Since L6740L uses external drivers to switch the power MOSFETs, check the selected

driver documentation for informations related to proper layout for this part.

11.2

Small signal components and connections

These are small signal components and connections to critical nodes of the application as

well as bypass capacitors for the device supply. Locate the bypass capacitor close to the

device and refer sensible components such as frequency set-up resistor ROSC, offset

resistor (both Sections) and OVP resistor ROVP to SGND. Star grounding is suggested:

connect SGND to PGND plane in a single point to avoid that drops due to the high current

delivered causes errors in the device behavior.

VSEN pin filtered vs. SGND helps in reducing noise injection into device and EN pin filtered

vs. SGND helps in reducing false trip due to coupled noise: take care in routing driving net

for this pin in order to minimize coupled noise.

Remote Buffer Connection must be routed as parallel nets from the FBG/FBR pins to the

load in order to avoid the pick-up of any common mode noise. Connecting these pins in

points far from the load will cause a non-optimum load regulation, increasing output

tolerance.

Locate current reading components close to the device. The PCB traces connecting the

reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up

of any common mode noise. It's also important to avoid any offset in the measurement and,

to get a better precision, to connect the traces as close as possible to the sensing elements.

Symmetrical layout is also suggested. Small filtering capacitor can be added, near the

controller, between VOUT and SGND, on the CSx- line when reading across inductor to allow

higher layout flexibility.

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