L6740L datasheet(19/44 Pages) STMICROELECTRONICS

19 / 44 page

L6740L

Hybrid CPU support and CPU_TYPE detection

19/44

transition for the addressed section(s) or, more in general, react to the sent command

accordingly. Refer to Figure 7, Table 8 and Table 9 for details about the Set VID Command.

L6740L is able to manage individual power OFF for both the Sections. The CPU may issue

a serial VID command to power OFF or power ON one Section while the other one remains

powered. In this case, the PWRGOOD signal remains asserted.

Figure 7.

SVI communications - Send byte

Table 8.

SVI send byte - Address and data phase description

bits

Description

Address phase

6:4

Always 110b.

Not Applicable, ignored.

CORE Section(1).

If set then the following data byte contains the VID code for CORE Section.

Assertion in both bit 1 and 0 will address the VID code to both CORE and NB simultaneously.

NB Section(1).

If set then the following data byte contains the VID code for NB Section.

Data phase

PSI_L Flag (Active low).When asserted, the VR is allowed to enter Power-Saving

mode. See Section 5.4.3.

6:0

VID Code. See Table 9.

SVC

SVD

START

110b

ACK

Slave Addressing

(7 Clocks)

654

WRITE

(1Ck)

ACK

(1Ck)

Data Phase

(8 Clocks)

ACK

(1Ck)

STOP

START

SLAVE ADDRESSING + W

ACK

DATA PHASE

ACK

STOP

BUS DRIVEN BY L6740L

BUS DRIVEN BY MASTER (CPU)

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