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WM8994ECS/R 数据表(PDF) 284 Page - Cirrus Logic

部件名 WM8994ECS/R
功能描述  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8994ECS/R 数据表(HTML) 284 Page - Cirrus Logic

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WM8994
284
Rev 4.6
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R517 (0205h)
AIF2
Clocking (2)
5:3
AIF2DAC_DIV
[2:0]
000
Selects the AIF2 input path sample rate relative to the AIF2
output path sample rate.
This field should only be changed from default in modes
where the AIF2 input path sample rate is slower than the
AIF2 output path sample rate.
000 = Divide by 1
001 = Divide by 1.5
010 = Divide by 2
011 = Divide by 3
100 = Divide by 4
101 = Divide by 5.5
110 = Divide by 6
111 = Reserved
2:0
AIF2ADC_DIV
[2:0]
000
Selects the AIF2 output path sample rate relative to the
AIF2 input path sample rate.
This field should only be changed from default in modes
where the AIF2 output path sample rate is slower than the
AIF2 input path sample rate.
000 = Divide by 1
001 = Divide by 1.5
010 = Divide by 2
011 = Divide by 3
100 = Divide by 4
101 = Divide by 5.5
110 = Divide by 6
111 = Reserved
Register 0205h AIF2 Clocking (2)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R520 (0208h)
Clocking (1)
4
TOCLK_ENA
0
Slow Clock (TOCLK) Enable
0 = Disabled
1 = Enabled
This clock is required for zero-cross timeout.
3
AIF1DSPCLK_E
NA
0
AIF1 Processing Clock Enable
0 = Disabled
1 = Enabled
2
AIF2DSPCLK_E
NA
0
AIF2 Processing Clock Enable
0 = Disabled
1 = Enabled
1
SYSDSPCLK_E
NA
0
Digital Mixing Processor Clock Enable
0 = Disabled
1 = Enabled
0
SYSCLK_SRC
0
SYSCLK Source Select
0 = AIF1CLK
1 = AIF2CLK
Register 0208h Clocking (1)



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