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WM8994ECS/R 数据表(PDF) 285 Page - Cirrus Logic

部件名 WM8994ECS/R
功能描述  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8994ECS/R 数据表(HTML) 285 Page - Cirrus Logic

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WM8994
Rev 4.6
285
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R521 (0209h)
Clocking (2)
10:8
TOCLK_DIV
[2:0]
000
Slow Clock (TOCLK ) Divider
(Sets TOCLK rate relative to 256kHz.)
000 = Divide by 256 (1kHz)
001 = Divide by 512 (500Hz)
010 = Divide by 1024 (250Hz)
011 = Divide by 2048 (125Hz)
100 = Divide by 4096 (62.5Hz)
101 = Divide by 8192 (31.2Hz)
110 = Divide by 16384 (15.6Hz)
111 = Divide by 32768 (7.8Hz)
6:4
DBCLK_DIV
[2:0]
000
De-bounce Clock (DBCLK) Divider
(Sets DBCLK rate relative to 256kHz.)
000 = Divide by 256 (1kHz)
001 = Divide by 2048 (125Hz)
010 = Divide by 4096 (62.5Hz)
011 = Divide by 8192 (31.2Hz)
100 = Divide by 16384 (15.6Hz)
101 = Divide by 32768 (7.8Hz)
110 = Divide by 65536 (3.9Hz)
111 = Divide by 131072 (1.95Hz)
2:0
OPCLK_DIV
[2:0]
000
GPIO Output Clock (OPCLK) Divider
000 = SYSCLK
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 6
101 = SYSCLK / 8
110 = SYSCLK / 12
111 = SYSCLK / 16
Register 0209h Clocking (2)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R528 (0210h)
AIF1 Rate
7:4
AIF1_SR [3:0]
1000
Selects the AIF1 Sample Rate (fs)
0000 = 8kHz
0001 = 11.025kHz
0010 = 12kHz
0011 = 16kHz
0100 = 22.05kHz
0101 = 24kHz
0110 = 32kHz
0111 = 44.1kHz
1000 = 48kHz
1001 = 88.2kHz
1010 = 96kHz
All other codes = Reserved
Note that 88.2kHz and 96kHz modes are supported for
AIF1 input (DAC playback) only.



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