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WM8994ECS/R 数据表(PDF) 289 Page - Cirrus Logic |
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WM8994ECS/R 数据表(HTML) 289 Page - Cirrus Logic |
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289 / 363 page ![]() WM8994 Rev 4.6 289 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R576 (0240h) FLL2 Control (1) 1 FLL2_OSC_EN A 0 FLL2 Oscillator enable 0 = Disabled 1 = Enabled (Note that this field is required for free-running FLL2 modes only) 0 FLL2_ENA 0 FLL2 Enable 0 = Disabled 1 = Enabled This should be set as the final step of the FLL1 enable sequence, ie. after the other FLL registers have been configured. Register 0240h FLL2 Control (1) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R577 (0241h) FLL2 Control (2) 13:8 FLL2_OUTDIV [5:0] 00_0000 FLL2 FOUT clock divider 000000 = Reserved 000001 = Reserved 000010 = Reserved 000011 = 4 000100 = 5 000101 = 6 … 111110 = 63 111111 = 64 (FOUT = FVCO / FLL2_OUTDIV) 2:0 FLL2_FRATIO [2:0] 000 FLL2 FVCO clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1XX = 16 Register 0241h FLL2 Control (2) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R578 (0242h) FLL2 Control (3) 15:0 FLL2_K [15:0] 0000_0000 _0000_000 0 FLL2 Fractional multiply for FREF (MSB = 0.5) Register 0242h FLL2 Control (3) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R579 (0243h) FLL2 Control (4) 14:5 FLL2_N [9:0] 00_0000_0 000 FLL2 Integer multiply for FREF (LSB = 1) Register 0243h FLL2 Control (4) |
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