WM8994ECSSLASHR datasheet(292/363 Pages) CIRRUS

292 / 363 page

WM8994

292

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R770 (0302h)

AIF1

Master/Slave

AIF1_TRI

AIF1 Audio Interface tri-state

0 = AIF1 pins operate normally

1 = Tri-state all AIF1 interface pins

Note that the GPIO1 pin is controlled by this register only

when configured as ADCLRCLK1.

AIF1_MSTR

AIF1 Audio Interface Master Mode Select

0 = Slave mode

1 = Master mode

AIF1_CLK_FRC

Forces BCLK1, LRCLK1 and ADCLRCLK1 to be enabled

when all AIF1 audio channels are disabled.

0 = Normal

1 = BCLK1, LRCLK1 and ADCLRCLK1 always enabled in

Master mode

AIF1_LRCLK_F

Forces LRCLK1 and ADCLRCLK1 to be enabled when all

AIF1 audio channels are disabled.

0 = Normal

1 = LRCLK1 and ADCLRCLK1 always enabled in Master

mode

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R771 (0303h)

AIF1 BCLK

8:4

AIF1_BCLK_DIV

[4:0]

0_0100

BCLK1 Rate

00000 = AIF1CLK

00001 = AIF1CLK / 1.5

00010 = AIF1CLK / 2

00011 = AIF1CLK / 3

00100 = AIF1CLK / 4

00101 = AIF1CLK / 5

00110 = AIF1CLK / 6

00111 = AIF1CLK / 8

01000 = AIF1CLK / 11

01001 = AIF1CLK / 12

01010 = AIF1CLK / 16

01011 = AIF1CLK / 22

01100 = AIF1CLK / 24

01101 = AIF1CLK / 32

01110 = AIF1CLK / 44

01111 = AIF1CLK / 48

10000 = AIF1CLK / 64

10001 = AIF1CLK / 88

10010 = AIF1CLK / 96

10011 = AIF1CLK / 128

10100 = AIF1CLK / 176

10101 = AIF1CLK / 192

10110 - 11111 = Reserved

WM8994ECS/R 数据表(PDF) 292 Page - Cirrus Logic

WM8994ECS/R 数据表(HTML) 292 Page - Cirrus Logic

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