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WM8994ECS/R 数据表(PDF) 291 Page - Cirrus Logic

部件名 WM8994ECS/R
功能描述  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8994ECS/R 数据表(HTML) 291 Page - Cirrus Logic

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WM8994
Rev 4.6
291
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
LRCLK1 rising edge (mode B)
6:5
AIF1_WL [1:0]
10
AIF1 Digital Audio Interface Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
Note - 8-bit modes can be selected using the
“Companding”
control bits.
4:3
AIF1_FMT [1:0]
10
AIF1 Digital Audio Interface Format
00 = Right justified
01 = Left justified
10 = I2S Format
11 = DSP Mode
Register 0300h AIF1 Control (1)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R769 (0301h)
AIF1 Control
(2)
15
AIF1DACL_SRC
0
AIF1 Left Receive Data Source Select
0 = Left DAC receives left interface data
1 = Left DAC receives right interface data
14
AIF1DACR_SR
C
1
AIF1 Right Receive Data Source Select
0 = Right DAC receives left interface data
1 = Right DAC receives right interface data
11:10
AIF1DAC_BOO
ST [1:0]
00
AIF1 Input Path Boost
00 = 0dB
01 = +6dB (input must not exceed -6dBFS)
10 = +12dB (input must not exceed -12dBFS)
11 = +18dB (input must not exceed -18dBFS)
8
AIF1_MONO
0
AIF1 DSP Mono Mode
0 = Disabled
1 = Enabled
Note that Mono Mode is only supported when AIF1_FMT =
11. The number of BCLK cycles per LRCLK frame must be
less the 2 x AIF1 Word Length.
4
AIF1DAC_COM
P
0
AIF1 Receive Companding Enable
0 = Disabled
1 = Enabled
3
AIF1DAC_COM
PMODE
0
AIF1 Receive Companding Type
0 = µ-law
1 = A-law
2
AIF1ADC_COM
P
0
AIF1 Transmit Companding Enable
0 = Disabled
1 = Enabled
1
AIF1ADC_COM
PMODE
0
AIF1 Transmit Companding Type
0 = µ-law
1 = A-law
0
AIF1_LOOPBAC
K
0
AIF1 Digital Loopback Function
0 = No loopback
1 = Loopback enabled (ADCDAT1 data output is directly
input to DACDAT1 data input).
Register 0301h AIF1 Control (2)



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