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CC1070-RTY1 数据表(PDF) 32 Page - Texas Instruments |
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CC1070-RTY1 数据表(HTML) 32 Page - Texas Instruments |
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32 / 57 page ![]() CC1070 SWRS043A Page 32 of 54 C6 [nF] C7 [pF] C8 [pF] R2 [kΩ] R3 [kΩ] PLL turn-on time [us] Comment 220 8200 2200 1.5 4.7 3200 Up to 4.8 kBaud data rate, 12.5 kHz channel spacing 100 3900 1000 2.2 6.8 2500 Up to 4.8 kBaud data rate, 25 kHz channel spacing 56 2200 560 3.3 10 1400 Up to 9.6 kBaud data rate, 50 kHz channel spacing 15 560 150 5.6 18 1300 Up to 19.2 kBaud data rate, 100 kHz channel spacing 3.9 120 33 12 39 1080 Up to 38.4 kBaud data rate, 150 kHz channel spacing 1.0 27 3.3 27 82 950 Up to 76.8 kBaud data rate, 200 kHz channel spacing 0.2 1.5 - 47 150 700 Up to 153.6 kBaud data rate, 500 kHz channel spacing Table 19. Typical PLL turn-on time to within ±10% of channel spacing for different loop filter bandwidths 14.4 PLL Lock Time versus Loop Filter Bandwidth If calibration has been performed the PLL lock time is the time needed for the PLL to lock to the desired frequency when going from one transmit frequency to the next by changing the F_REG bit in the MAIN register. The PLL lock time depends on the PLL loop filter bandwidth. Table 20 gives the PLL lock time for different PLL loop filter bandwidths. PLL lock time [us] C6 [nF] C7 [pF] C8 [pF] R2 [kΩ] R3 [kΩ] 1 2 Comment 220 8200 2200 1.5 4.7 180 1300 Up to 4.8 kBaud data rate, 12.5 kHz channel spacing 100 3900 1000 2.2 6.8 270 830 Up to 4.8 kBaud data rate, 25 kHz channel spacing 56 2200 560 3.3 10 140 490 Up to 9.6 kBaud data rate, 50 kHz channel spacing 15 560 150 5.6 18 70 230 Up to 19.2 kBaud data rate, 100 kHz channel spacing 3.9 120 33 12 39 50 180 Up to 38.4 kBaud data rate, 150 kHz channel spacing 1.0 27 3.3 27 82 15 55 Up to 76.8 kBaud data rate, 200 kHz channel spacing 0.2 1.5 - 47 150 14 28 Up to 153.6 kBaud data rate, 500 kHz channel spacing Table 20. Typical PLL lock time to within ±10% of channel spacing for different loop filter bandwidths. 1) 1 channel step, 2) 1 MHz step 15 VCO Current Control The VCO current is programmable and should be set according to operating frequency and output power. Recommended settings for the VCO_CURRENT bits in the VCO register are shown in the register overview (page 40) and also given by SmartRF® Studio. The VCO current for frequency FREQ_A and FREQ_B can be programmed independently. The bias current for the PA buffers is also programmable. The BUFF_CURRENT register controls this current. |
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