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CC1070-RTY1 数据表(PDF) 50 Page - Texas Instruments |
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CC1070-RTY1 数据表(HTML) 50 Page - Texas Instruments |
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50 / 57 page  CC1070 SWRS043A Page 50 of 54 TEST4 Register (24h, for test only) REGISTER NAME Default value Active Description TEST4[7] CHP_DISABLE 0 H Disable normal charge pump operation TEST4[6] CHP_TEST_UP 0 H Force charge pump to output “up” current TEST4[5] CHP_TEST_DN 0 H Force charge pump to output “down” current TEST4[4:3] - reserved TEST4[2] - reserved TEST4[1] - reserved TEST4[0] - reserved TEST5 Register (25h, for test only) REGISTER NAME Default value Active Description TEST5[7] F_COMP_ENABLE 0 H Enable frequency comparator output F_COMP from phase detector TEST5[6] SET_DITHER_CLOCK 1 H Enable dithering of delta-sigma clock TEST5[5] - reserved TEST5[4] - reserved TEST5[3] - reserved TEST5[2] - reserved TEST5[1:0] - reserved TEST_NFC Register (28h, for test only) REGISTER NAME Default value Active Description TEST_NFC[7:6] CAL_WTIME_2 0 - Wait time vcdac, vco_array, chp_current calibrations. Encoding: 0 – 1 clock cycle 1 – 2 clock cycles 2 – 6 clock cycles 3 – 50 clock cycles TEST_NFC[5:4] CAL_WTIME_1 1 - Wait time vco_cal_current calibration. Encoding: 0 – 1 clock cycle 1 – 12 clock cycles 2 – 63 clock cycles 3 – 127 clock cycles TEST_NFC[3:0] CAL_DEC_LIMIT 5 - Calibration decision limit in new frequency comparator STATUS Register (40h, read only) REGISTER NAME Default value Active Description STATUS[7] CAL_COMPLETE - H Set to 0 when PLL calibration starts, and set to 1 when calibration has finished STATUS[6] - - reserved STATUS[5] LOCK_INSTANT - H Instantaneous PLL lock indicator STATUS[4] LOCK_CONTINUOUS - H PLL lock indicator, as defined by LOCK_ACCURACY. Set to 1 when PLL is in lock STATUS[3] - reserved STATUS[2] LOCK - H Logical level on LOCK pin STATUS[1] DCLK - H Logical level on DCLK pin STATUS[0] DIO - H Logical level on DIO pin |
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