CC1070-RTY1 datasheet(12/57 Pages) TI2

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CC1070

SWRS043A

Page 12 of 54

Pin Assignment

Table 8 provides an overview of the

CC1070 pinout.

The

CC1070 comes in a QFN20 type

package.

PCLK 1AVDD

PA_EN

AVDD

RF_OUT

R_BIAS

DVDD 5

PDO 4

PDI 3

DI 2

AGND

Exposed die

attached pad

Figure 1.

CC1070 package (top view)

Pin no.

Pin name

Pin type

Description

AGND

Ground (analog)

Exposed die attached pad. Must be soldered to a solid ground

plane as this is the ground connection for all analog modules See

page 39 for more details.

PCLK

Digital input

Programming clock for SPI configuration interface

Digital input

Data input in transmit mode

PDI

Digital input

Programming data input for SPI configuration interface

PDO

Digital output

Programming data output for SPI configuration interface

DVDD

Power (digital)

Power supply (3 V typical) for digital modules and digital I/O

DCLK

Digital output

Clock for transmit data

LOCK

Digital output

PLL Lock indicator, active low. Output is asserted (low) when PLL

is in lock. The pin can also be used as a general digital output.

XOSC_Q1

Analog input

Crystal oscillator or external clock input

XOSC_Q2

Analog output

Crystal oscillator

AVDD

Power (analog)

Power supply (3 V typical) for crystal oscillator and bias generator

(double bonded).

R_BIAS

Analog output

Connection for external precision bias resistor (82 k

Ω, ± 1%)

RF_OUT

RF output

RF signal output to antenna

AVDD

Power (analog)

Power supply (3 V typical) for LO buffers, prescaler and PA first

stage

PA_EN

Digital output

General digital output. Can be used for controlling an external PA,

if higher output power is needed.

AVDD

Power (analog)

Power supply (3 V typical) for VCO

Analog input

VCO control voltage input from external loop filter

AVDD

Power (analog)

Power supply (3 V typical) for charge pump and phase detector

CHP_OUT

Analog output

PLL charge pump output to external loop filter

DVDD

Power (digital)

Power supply connection (3 V typical) for digital modules

PSEL

Digital input

Programming chip select, active low, for configuration interface.

Internal pull-up resistor.

Table 8. Pin assignment overview

Note:

DCLK, DI and LOCK are high-impedance

(3-state) in power down (BIAS_PD = 1 in

the MAIN register).

The exposed die attached pad must be

soldered to solid ground plane as this is

the main ground connection for the chip.

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