ADS1675 datasheet(20/40 Pages) TI2

20 / 40 page

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

NormalizedFrequency(f /f

)

IN DATA

DRATE= ‘

’

000

DRATE= ‘011’

DRATE= ‘101’

DRATE= ‘100’

1.4

1.2

1.0

0.8

0.6

0.4

0.2

Conversions(1/f

)

DRDY-FR

DRATE=000,

001,010

DRATE=011

DRATE=100

DRATE=101

100

120

-140

1.0

2.0

NormalizedFrequency(f /f

)

IN CLK

3.0

0.5

1.5

2.5

Data1

Data2

Data3

Data4

Data0

DRDY

LL-FR

Changeon

AnalogInputs

Fully-SettledDataAvailable

forDRATE=000 ,001,010

(1)

ADS1675

SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010

www.ti.com

It is important to note, however, that the absolute

settling time of the Low-Latency path does not

change when using the fast response configuration.

Changes on the input signal during conversions after

the initial settling require multiple cycles to fully settle.

To help illustrate this requirement, consider a change

on the inputs as shown in Figure 42, where START is

assumed to have been taken high before the input

voltage was changed.

The readings after a step change in the input is

settled as shown in Figure 39 for all different data

rates.

Figure 40. Frequency Response of Low-Latency

Filter in Fast-Response Configuration

Figure 39. Step Response for Low-Latency Filter

with Fast-Response Configuration

Frequency Response

Figure 40 shows the frequency response for the

Figure 41. Extended Frequency Response of

Low-Latency filter path normalized to the output data

Low-Latency Path

rate, fDATA. The overall frequency response repeats at

the modulator sampling rate, which is the same as

the input clock frequency. Figure 41 shows the

response with the fastest data rate selected (4 MSPS

when fCLK = 32MHz).

NOTE: START pin held high previous to change on analog inputs.

(1) Refer to Figure 39 for other modes.

Figure 42. Settling Example with the Low-Latency Filter in Fast-Response Configuration

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