ADS1675 datasheet(6/40 Pages) TI2

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ADS1675

SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010

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TERMINAL FUNCTIONS (continued)

NAME

NO.

FUNCTION

DESCRIPTION

Configure Low-Latency digital filter.(1)

LL_CONFIG

Digital input

If LL_CONFIG = '0', then single-cycle settling is selected.

If LL_CONFIG = '1', then fast-response is selected.

Digital filter path selection.

FPATH

Digital input

If FPATH = '0', then path is Wide-Bandwidth.

If FPATH = '1', then path is Low-Latency.

DRATE[2:0]

34-36

Digital input

Data rate selection

START

Digital input

Start convert, reset, and synchronization control input

Digital input

Chip select; active low

OTRD

Digital output

Digital filter out-of-range indicator

OTRA

Digital input

Analog input out-of-range indicator

Negative shift clock output.

SCLK

Digital output

If SCLK_SEL = '0', then SCLK is the complementary shift clock output.

If SCLK_SEL = '1', then SCLK always output is 3-state.

Positive shift clock output.

SCLK

Digital input/output

If SCLK_SEL = '0', then SCLK is an output.

If SCLK_SEL = '1', then SCLK is an input.

DOUT

Digital output

Negative LVDS serial data output

DOUT

Digital output

Positive LVDS serial data output

DRDY

Digital output

Negative data ready output

DRDY

Digital output

Positive data ready output

CLK

Digital input

Master clock input

CAP1

Analog

Terminal for 1mF external bypass capacitor

VREFN

60, 61

Analog

Negative reference voltage. Short to analog ground

CAP2

Analog

Terminal for 1mF external bypass capacitor

VREFP

63, 64

Analog

Positive reference voltage

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