ADS1675 datasheet(7/40 Pages) TI2

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LSCLKDC

DRDY

MSB

LSB

MSB

D UT

S LK

LSCLKDR

LDOPD

LDRPW

LSCLK

CLK

SCLK

START

DRDY

STCLK

LSCLKDR

LSCLK

LCLKSCLK

SETTLE

LPLLSTL

CLK

SETTLE

ADS1675

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SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010

TIMING CHARACTERISTICS

(1) High-speed LVDS valid only for DRATE = 100 and DRATE = 101.

(2) Timing shown is the single-end version of the LVDS signal pairs.

Figure 1. High-Speed LVDS Data Retrieval Timing

TIMING REQUIREMENTS: High-Speed LVDS

At TA = –40°C to +85°C, and DVDD = 2.85V to 3.15V.

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

tLDRPW

DRDY pulse width

tLSCLKs

tLSCLKDR

SCLK to DRDY delay

tLDOPD

Valid data delay time from serial shift clock

1.5

2.5

tLSCLK

Period of LVDS serial shift clock (SCLK)

0.33

tCLKs

tLSCLKDC

Shift clock duty cycle

tCLK

CLK period (1/fCLK)

31.25

tLCLKSCLK

Delay from rising edge of CLK to rising edge of SCLK

tLPLLSTL

PLL settling time

tSTCLK

Setup time, rising edge of START to falling edge of CLK

–3

tSETTLE

Digital filter settling time

See Table 5 and Table 6

Figure 2. PLL Timing

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