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ADS1675 数据表(PDF) 5 Page - Texas Instruments |
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ADS1675 数据表(HTML) 5 Page - Texas Instruments |
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5 / 40 page ![]() 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DVDD DGND DRDY DRDY DOUT DOUT SCLK SCLK OTRA OTRD CS START DRATE[0] DRATE[1] DRATE[2] FPATH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AVDD AGND AGND AINN AINP AGND AVDD RBIAS AGND AGND AVDD AVDD VCM DGND DGND DGND 64 63 62 61 60 59 58 57 56 55 54 17 18 19 20 21 22 23 24 25 26 27 53 52 51 50 49 28 29 30 31 32 ADS1675 ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 DEVICE INFORMATION TQFP PACKAGE TQFP-64 (TOP VIEW) TERMINAL FUNCTIONS PIN NAME NO. FUNCTION DESCRIPTION 1, 7, 11, 12, 53, AVDD Analog Analog supply 58 2, 3, 6, 9, 10, AGND Analog Analog ground 54, 56, 57 AINN 4 Analog input Negative analog input AINP 5 Analog input Positive analog input RBIAS 8 Analog Analog bias setting resistor VCM 13 Analog Terminal for external bypass capacitor connection to internal common-mode voltage 14-20, 25, 26, DGND Digital Digital ground 31, 47, 50, 51 RSV2 21 Reserved Short pin to digital ground RSV1 22 Reserved Short pin to digital supply 23, 24, 27, 48, DVDD Digital Digital supply 49, 52 PDWN 28 Digital input Power-down control, active low Shift-clock source select.(1) SCLK_SEL 29 Digital input If SCLK_SEL = '0', then SCLK is internally generated. If SCLK_SEL = '1', then SCLK must be externally generated. Serial interface select.(1) LVDS 30 Digital input If LVDS = '0', then interface is LVDS-compatible. If LVDS = '1', then interface is CMOS-compatible. (1) Option not available in high-speed mode. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): ADS1675 |
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