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ADS1675 数据表(PDF) 8 Page - Texas Instruments

部件名 ADS1675
功能描述  4MSPS, 24-Bit Analog-to-Digital Converter
PDF  40 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

ADS1675 数据表(HTML) 8 Page - Texas Instruments

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CLK
DRDY
t
CLK
t
LSCLK
SCLK
internal
t
LDOPD
t
DRSCLK
DOUT
MSB
LSB
t
LDRPW
t
LCLKDR
CS
t
SPWH
t
DC
ADS1675
SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010
www.ti.com
Figure 3. Low-Speed Mode Data Retrieval Timing with Internal SCLK (SCLK_SEL = 0)
TIMING REQUIREMENTS: Internal SCLK
At TA = –40°C to +85°C, and DVDD = 2.85V to 3.15V.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
tDC
CLK duty cycle
47
50
53
%
tSPWH
SCLK pulse width high
15.6
ns
tCLK
CLK period (1/fCLK)
31.25
ns
tCLKDR
CLK to DRDY delay
23
30
ns
tLDRPW
DRDY pulse width
1
tCLK
tDRSCLK
Internal SCLK Rising to DRDY active edge
2.2
4.4
ns
tLSCLK
Internally-generated SCLK rising edge to DRDY rising edge
1
tCLK
tLDOPD
Rising edge of SCLK to new valid data output (propagation delay)
1.9
2.8
ns
8
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Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1675



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