L9942 datasheet(7/40 Pages) STMICROELECTRONICS

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L9942

Block diagram and pin information

Doc ID 11778 Rev 7

7/40

Table 2.

Pin description

Symbol

Function

1, 12, 13,

PGND

Power ground: All pins PGND are internally connected to the heat slug.

Important: All pins of PGND must be externally connected!

3, 10, 15,

Power supply voltage (external reverse protection required): For EMI

reason a ceramic capacitor as close as possible to PGND is recommended.

Important: All pins of VS must be externally connected!

2, 23

QA1,QA

Fullbridge-outputs An: The output is built by a high-side and a low-side

switch, which are internally connected. The output stage of both switches is

a power DMOS transistor. Each driver has an internal reverse diode (bulk-

drain-diode: highside driver from output to VS, low-side driver from PGND to

output). This output is overcurrent protected.

11, 14

QB1,QB

Fullbridge-outputs Bn: The output is built by a highside and a low-side

switch, which are internally connected. The output stage of both switches is

a power DMOS transistor. Each driver has an internal reverse diode (bulk-

drain-diode: highside driver from output to VS, low-side driver from PGND to

output). This output is overcurrent protected.

CLK

SPI clock input: The input requires CMOS logic levels. The CLK input has

a pull-down current. It controls the internal shift register of the SPI.

Serial data input: The input requires CMOS logic levels. The DI input has a

pull-down current. It receives serial data from the microcontroller. The data

is a 16bit control word and the most significant bit (MSB, bit 0) is transferred

first.

CSN

Chip Select Not input The input requires CMOS logic levels. The CSN

input has a pull-up current. The serial data transfer between device and

micro controller is enabled by pulling the input CSN to low level.

SPI data output: The diagnosis data is available via the SPI and it is a

tristate-output. The output is CMOS compatible will remain highly resistive,

if the chip is not selected by the input CSN (CSN = high)

PWM

PWM output This CMOS compatible output reflects the current duty cycle

of the internal PWM controller of bridge A. It is an high resistance output

until VCC has reached minimum voltage ore can switched off via the SPI

command.

STEP

Step clock input: The input requires CMOS logic levels. The STEP input

has a pull-down current. It is clock of up and down counter of control

position.

Charge Pump Output: A ceramic capacitor (e.g.100 nF) to VS can be

connected to this pin to buffer the charge-pump voltage.

GND

Ground: Reference potential besides power ground e.g. for reference

resistor RREF. From this pin exist a resistive path via substrate to PGND.

TEST

Test input The TEST input has a pull-down current. Pin used for production

test only. In the application it must be connected to GND.

VCC

Logic supply voltage: For this input a ceramic capacitor as close as

possible to GND is recommended.

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