L9942 datasheet(21/40 Pages) STMICROELECTRONICS

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L9942

Functional description of the logic with SPI

Doc ID 11778 Rev 7

21/40

Functional description of the logic with SPI

4.1

Motor stepping clock input (STEP)

Rising edge of signal STEP is latched. It is synchronized by internal clock. At next start of a

new PWM cycle the new values of output current limit are used to drive motor in next

position. Before start new motor step this signal has to be low for at least two internal clock

periods to reset latch.

4.2

PWM output (PWM)

This output reflects the current duty cycle of the internal PWM controller of bridge A. High

level indicates on state to increase current through load and low level is in off state so load

current decreases depending on chosen decay mode.

4.3

Serial peripheral interface (SPI)

This device uses a standard 16 bit SPI to communicate with a microcontroller. The SPI can

be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0

and CPHA = 0.

For this mode, input data is sampled by the low to high transition of the clock CLK, and

output data is changed from the high to low transition of CLK.

A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect an

internal error flag of the device which is a logical-or of all status bits in the Status Register

(reg 7) and in the current profile register 4 (reg 6). The microcontroller can poll the status of

the device without the need of a full SPI-communication cycle.

4.4

Chip select not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the

output pin (DO) will be in high impedance state. A low signal will activate the output driver

and a serial communication can be started. The state when CSN is going low until the rising

edge of CSN will be called a communication frame.

4.5

Serial data in (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI will be

sampled at the rising edge of the CLK signal and latched into an internal 16 bit shift register.

The first 3 bit are interpreted as address of the data register. At the rising edge of the CSN

signal the contents of the shift register will be transferred to the selected data register. The

writing to the register is only enabled if exactly 16 bits are transmitted within one

communication frame (i.e. CSN low). If more or less clock pulses are counted within one

frame the complete frame will be ignored. This safety function is implemented to avoid an

activation of the output stages by a wrong communication frame.

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