L9942

Appendix

Doc ID 11778 Rev 7

33/40

7

Appendix

7.1

Stall detection

The L9942 contains logic blocks designed to detect a motor stall caused by excessive

mechanical load.During a motor stall condition the load current rises much faster than

during normal operation. The L9942 measures this time and compares it to a programmed

value.

This is done by summing the PWM on times for one full quadrant. For a full wave stepping

this is just one value (step 0). For microstepping this includes 8 separate values added

together, one for each step. This measurement is only done on phase A during the

quadrants where the current is increasing naturally (quadrants 1 and 3 of Figure 15); e.g.

stall detection is active during phase counter values 1 to 8 and 17 to 24 for DIR=0. During

the quadrants where the current is decreasing fast decay recirculation interferes with

accurate measurement of this time. If the sum of the PWM on time is less than a

programmed threshold stored in D0-D7, stall is detected and indicated as a logic “1” in the

stall (ST) bit found in register 6 bit 8 (Figure 15 bottom). If bit 11 of register 6 is set to logical

“1” then the ST bit is mirrored to the PWM pin providing detection externally.The register

values DT7-DT0 store the threshold value in 16us intervals. These bits can be found

interstitially in register 3 (D0, D1), register4 (D2, D3, D4) and register5 (D5, D6, D7).

Care should be taken when deciding the threshold timing. Motor current slew rates are

dependant on the driving voltage, the actual speed of the motor, the back EMF of the motor

as well as the motor and the inductance. Be sure to set your threshold well away from what

can be seen in normal operation at any temperature.

7.2

Step clock input

The Step clock input allows to run one device in micro-step mode, or several devices

simultaneously with cost effective 8 bit µController. In case of the L9942, the SPI

communication link provides only the settings for motor operation mode. Motor commutation

as high duty process is outsourced to a parallel driven pin. Without this step clock input, the

SPI command would also have to clock the motor, leading to a high SPI speed. For full

micro-step operation or simultaneous motor drive, an 8 bit µController could be rapidly

overloaded.

7.3

Load current control and detection of overcurrent (shortages

at outputs)

The L9942 controls load current in the two full bridges by using a pulls with modulation

(PWM) regulator. The mirrored output current of active HS switch is compared with a

programmed reference current (e.g. in figure A2 HSA1 and HSB2). Bridge is switched off if

current has exceeded the programmed limit value. A second comparator of the related LS

switch uses the mirrored load current to detect an overcurrent to ground during ON state of

bridges (e.g. in Figure 16 LSA2 and LSB1). The event of shortage from output to supply

voltage VS is detectable, but short current between outputs is limited through PWM

controller and so an overcurrent failure will not occur.

Load currents decrease more or less fast during OFF state of bridges depending on

selected decay mode. Slow decay mode is released by activating the HS switches of the