L9942 datasheet(10/40 Pages) STMICROELECTRONICS

10 / 40 page

Device description

L9942

10/40

Doc ID 11778 Rev 7

2.5

Temperature warning and thermal shutdown

If junction temperature rises above Tj TW a temperature warning flag is set which is

detectable via the SPI. If junction temperature increases above the second threshold Tj SD,

the thermal shutdown bit will be set and power DMOS transistors of all output stages are

switched off to protect the device. In order to reactivate the output stages the junction

temperature must decrease below Tj SD -Tj SD HYS and the thermal shutdown bit has to be

cleared by the microcontroller.

2.6

Inductive loads

Each half bridge is built by an internally connected highside and a low-side power DMOS

transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be

driven without external free-wheeling diodes. In order to reduce the power dissipation during

free-wheeling condition the PWM controller will switch-on the output transistor parallel to the

freewheeling diode (synchronous rectification).

2.7

Cross-current protection

The four half-brides of the device are cross-current protected by an internal delay time

depending on the programmed slew rate. If one driver (LS or HS) is turned-off then

activation of the other driver of the same half bridge will be automatically delayed by the

cross-current protection time.

2.8

PWM current regulation

An internal current monitor output of each high-side and low-side transistor sources a

current image which has a fixed ratio of the instantaneous load current. This current images

are compared with the current limit in PWM control. Range of limit can reach from

programmed full scale value (register1 DAC Scale) down belonging LSB value of 5 bit DAC

(register1 DAC Phase x). The data of the two 5 bit DACs comes form set up in 9 current

profiles (register2 to 6). If signal changes to logic high at pin STEP then 2 current profiles

are moved in register1 for DAC Phase A and B. Number of profile depends on phase

counter reading and direction bit in register0 (Figure 7). The bridges are switched on until

the load current sensed at HS switch exceeds the limit. Load current comparator signal is

used to detect open load or overcurrent condition also.

2.9

Decay modes

During off-time the device will use one of several decay modes programmable by SPI

(Figure 4 top). In slow decay mode HS switches are activated after cross current protection

time for synchronous rectification to reduce the power dissipation (Figure 4 detail A). In fast

decay opposite half bridge will switched on after cross current protection time, that is same

like change in the direction. For mixed decay the duration of fast decay period before slow

decay can be set to a fixed time (Figure 4 detail B continuous line) or is triggered by under-

run of the load current limit (Figure 4 detail B dashed line), that can be detected at LS

switch. The special mode where the actual phase counter value is taken into account to

select the decay mode is called auto decay (e.g. in Figure 3 Micro Stepping DIR=1). If the

absolute value of the current limit is higher as during step before then PWM control uses

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