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L9942 数据表(PDF) 30 Page - STMicroelectronics |
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L9942 数据表(HTML) 30 Page - STMicroelectronics |
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30 / 40 page ![]() Logic with SPI - electrical characteristics L9942 30/40 Doc ID 11778 Rev 7 6.6 STEP timing Figure 10. Transfer timing diagram Figure 11. Input timing Table 26. STEP timing Symbol Parameter Test condition Min. Typ. Max. Unit tSTEPmin (1) STEP low or high time - 2 - - µs 1. Parameter guaranteed by design. A2 A1 time time time time time CSN high to low: DO enabled actual data DI: data will be accepted on the rising edge of CLK signal new data CSN CLK DI DO Control and Status Register DO: data will change on the falling edge of CLK signal status information fault bit CSN low to high: actual data is transfered to registers old data 12 3 4 5 6 78 9 10 11 012 13 14 15 1 0 actual data A1 A0 D12 D11 D10 D9 D8 D7 D6 D5 D4 A2 D3 D2 D1 D0 D0 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 t CSN_HI,min fault bit 0.8 VCC 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC Valid Valid CSN CLK DI t set CSN t CLKH t set CLK t CL KL t hold DI t set DI t CLK |
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