FC106

Revision 1.2

10/32

September 98

When EWRAP is high, the output of the transmitter is sent directly to the input of the

receiver.

3.6

Serializer latches and XOR-tree

The parallel data words TX[0:9] are individually sampled using the clocks provided by the

DLL Clock Generator. The outputs of these serializer latches are merged through an

Exclusive-OR tree, in order to generate the output data bit streams.

3.7

Serial input multiplexer

The Input Multiplexer supports the internal loopback of the high speed serial signal for test

purposes.

In normal operation, EWRAP is set low. The serial output data stream is placed at TX+/TX-

outputs, and the serial data accepted at RX+/RX- is transmitted to the deserializer block.

When wrap-mode is activated by setting EWRAP high, the serial data generated by the

serializer block is internally wrapped to the input of the deserializer block.

3.8

Deserializer functional description

The FC106 deserializer operates at signaling rates up to 1.0625 Gb/s, as specified in the

Fibre Channel standard. It extracts the clock and retimes the data from the serial bit stream.

The serial bit stream should be encoded as 10-bit characters (for example the 8B/10B code

for Fibre Channel) which provide a transition density greater than 10%. The retimed serial bit

stream is converted into a 10-bit parallel output word. The FC106 has internal DLL based

clock recovery circuit which requires no external components.

When the DLL of the serializer clock multiplier is locked to the expected data rate (defined by

REFCLK), the retiming acquisition time (to lock to the incoming serial data stream) is less

than 3 microseconds.

The FC106 provides byte and data word alignment using a comma symbol recognition

mechanism.

The 7-bit comma symbol is defined in Fibre Channel specification as a [0:6]= 0011111. This

pattern is only contained within special characters known as K28.1, K28.5 and K28.7

defined specifically for synchronization by Fibre Channel.

Serial data is received on the RX+ and RX- pins. The DLL clock recovery circuit will lock to

the data stream if the clock to be recovered is within 0.01% of the expected data rate. For