FC106

Revision 1.2

20/32

September 98

6

Timing Specifications

All AC measurements are made from the reference voltage level of the clock (1.4 volts), to

the valid input or output data levels.

6.1

Transmit interface timing and latency

Figure 6.1

Transmit interface timing and latency

Table 6.1

Transmit interface timing characteristics

Parameter

Description

Min

Typ

Max

Units

Reference clock frequency

100

106.25 110

MHz

F

tol

Frequency tolerance (dispersion between

REFCLK of transmitter and receiver chips)

100

-

+ 100

ppm

T

r

REFCLK Clock Rise Time (0.8 to 2V)

0.6

-

2.4

nS

T

f

REFCLK Clock Fall Time (0.8 to 2V)

0.6

-

2.4

nS

CLKJIT

REFCLK Jitter

40

pS

DT

REFCLK duty Cycle

40

-

60

%

Tsu_tx

Data set-up to a rising edge of REFCLK

0

-

-

ns

Th_tx

Data hold after a rising edge of REFCLK

1.5

-

-

ns

TX-Tr,Tf

Parallel data rise and fall time (10 pF load)

0.6

-

3

ns

Data Emission Latency (delay from the initial

10-bit word load to the serial transmission of bit 0)

-

-

1 REFCLK

cycle + 8 ns

VALID

DATA 3

TX[0:9]

REFCLK

Tsu_tx

Th_tx

VALID

DATA 1

VALID

DATA 2

1.4V

1.4V

2.0V

0.8V

TX+

bit 0 of parallel in-

put (TX0 of DATA 1)