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FC106 数据表(PDF) 27 Page - STMicroelectronics

部件名 FC106
功能描述  Fibre Channel Transceiver 1.0625 GBaud
PDF  32 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

FC106 数据表(HTML) 27 Page - STMicroelectronics

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FC106
Revision 1.2
27/32
September 98
Vdd/TRSTN
18
(I)
pu
Must be tied to Vdd.
Reset pin
for JTAG
EWRAP
19
I
pd
When tied to Vdd, causes the chip to internally
loop serialized transmit data to the deserializer.
Vdd/TMS
20
(I)
pu
Must be tied to Vdd.
Test mode
select for
JTAG
Vss
21
-
-
Ground Pin
REFCLK
22
I
pd
Reference clock frequency 106.25 MHz
Vdd
23
I
-
Power Pin
EN_CDET
24
I
pu
Enables the chip to perform the byte alignment
function when HIGH.
TEST
ENABLE
25
I
pd
Must be tied to GND.
Tie to Vdd
for AT PG
NC/TDO
26
(O)
-
Not connected
JTAG scan
out
NC
27
-
-
Not connected
Vdd/AT
28
(I)
pu
Must be tied to Vdd.
Places the
chip in
auto test
mode
when
LOW.
Vdd
29
-
Power Pin
RBC[1]
30
O
-
Receive byte clock used by the protocol to
register byte 0 and 2 of the receive parallel data.
RBC[0]
31
O
-
Receive byte clock used by the protocol to
register byte 1 and 3 of the receive parallel data.
Vss
32
-
-
Ground Pin
Vss
33
-
-
Ground Pin
RX[9]
34
O
-
Bit 9 of parallel receive data (last bit received)
RX[8]
35
O
-
Bit 8 of parallel receive data
RX[7]
36
O
-
Bit 7 of parallel receive data
Vdd
37
-
-
Power Pin
RX[6]
38
O
-
Bit 6 of parallel receive data
RX[5]
39
O
-
Bit 5 of parallel receive data
RX[4]
40
O
-
Bit 4 of parallel receive data
RX[3]
41
O
-
Bit 3 of parallel receive data
Vdd
42
-
-
Power Pin
Pin Name
Pin #
I/O
pull up/
down
Description in standard running conditions
TEST
pins



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