FC106

Revision 1.2

11/32

September 98

example, if the REFCLK used is 106.25 MHz, then the incoming data serial signaling rate

must be 1.0625

± 0.0001 Gb/s.

The FC106 provides 2 TTL recovered clocks RBC[0] and RBC[1], which are both driven at a

frequency of one twentieth of the serial signaling rate. These clocks are generated by the

clock recovery DLL, which is phase locked to the serial data. RBC[1] is 180

° out of phase

with RBC[0]. If serial data is not present, or does not meet the required transition density or

signaling rate, the RBC frequencies will be half of the expected recovered clock frequency

(defined by REFCLK). This function replaces the optional LCK_REF signal that is specified

in the Fibre Channel 10-bit interface. When no data is present, phase adjustments are

required for switching between a locking to incoming data and locking to REFCLK. The

specification on output clocks RBC[0:1] is maintained during these adjustments.The clock

periods are not truncated.

The serial data is retimed and deserialized. Parallel data is loaded into the output register,

and therefore accessible on the output data port. For Fibre Channel use, bytes 1 and 3 of the

receive data word will be accessible on the rising edge of RBC[0], and bytes 0 and 2 on the

rising edge of RBC[1].

When EN_CDET is set high, the FC106 examines serial data for the presence of a positive

disparity comma symbol (0011111). Improper alignment occurs when a comma symbol

straddles a 10-bit boundary or is not aligned within the 10-bit transmission character. Proper

alignment is reached by shifting the boundary of the parallel output.

At power up the FC106 will not be in synchronization and data alignment is not established.

The COM_DET output signal is then set low. When a comma symbol is detected, COM_DET

is set high (if EN_CDET is already set high). COM_DET will go high only during a cycle in

which RBC[1] is rising (see Section 6.2.2:

Receive interface timing on page 23 for precise

timing).

Note that if EN_CDET is set low, but a comma is detected while the input stream is already

word-aligned, COM_DET will be set high again.

3.9

Bit alignment

The alignment block aligns the incoming data bit stream and the reference clocks generated

by the DLL Clock Generator. It compensates for clock frequency dispersions between the

crystals generating the respective reference clocks REFCLK of the transmitting and

receiving chips.