FC106

Revision 1.2

26/32

September 98

7.2

Pin functions

Table 7.2

Pin functions

TX[0:9]

CMOS

TX[0:9] is the 10-bit parallel transmit data presented to the chip for serial-

ization and transmission onto the media. The order of transmission is TX[0]

through to TX[9].

CMOS

These pins are used to control the input and output impedance in accor-

dance with the configuration outlined in Section 3.13:

I/O impedance con-

trol on page 14.

1.

indicates signals that are not included in the Fibre Channel 10-Bit Interface Specification.

Pin Name

Pin #

I/O

pull up/

down

Description in standard running conditions

TEST

pins

1

-

-

Ground Pin

TX[0]

2

I

pd

Bit 0 of parallel transmit data (first bit sent)

TX[1]

3

I

pd

Bit 1 of parallel transmit data

TX[2]

4

I

pd

Bit 2 of parallel transmit data

5

-

-

Power Pin

TX[3]

6

I

pd

Bit 3 of parallel transmit data

TX[4]

7

I

pd

Bit 4 of parallel transmit data

TX[5]

8

I

pd

Bit 5 of parallel transmit data

TX[6]

9

I

pd

Bit 6 of parallel transmit data

10

-

-

Power Pin

TX[7]

11

I

pd

Bit 7 of parallel transmit data

TX[8]

12

I

pd

Bit 8 of parallel transmit data

TX[9]

13

I

pd

Bit 9 of parallel transmit data (last bit sent)

14

-

-

Ground Pin

15

(I)

pd

Must be tied to GND during normal operation.

During power up, an internal circuit will

automatically reset the chip. Nevertheless RS

allows a forced reset (when high), during normal

operation.

External

reset

NC/TDI

16

(I)

pd

Not connected

JTAG

scan in

NC/TCK

17

(I)

pd

Not connected

Test clock

pin for

JTAG

Pin

Level

Description